Hot-Carrier Degradation in Power LDMOS: Drain Bias Dependence and Lifetime Evaluation

Abstract

In this brief, we present an analysis of the degradation induced by hot-carrier stress in new generation power lateral double-diffused MOSFET (LDMOS) transistors. When a relatively high drain voltage is applied during the ON-state regime, high energetic and/or multiple cold electrons are recognized as the main source of degradation affecting the LDMOS lifetime: the latter is usually extrapolated at typical operating drain voltages. Hence, the extrapolation criterion is particularly critical, and different models have been proposed in the past and discussed in this brief. In particular, the dependence of ON-resistance degradation ( $R_{\mathrm{\scriptscriptstyle ON}}$ ) on drain bias is investigated, and a simplified extrapolation model, accounting for the saturation effects of $R_{\mathrm{\scriptscriptstyle ON}}$ at long stress times, is proposed and validated by comparison with experiments and advanced physics-based TCAD simulations, confirming the ability to accurately estimate lifetime on devices featuring short-circuited source–body contacts.