Novel Superjunction LDMOS (>950 V) With a Thin Layer SOI

Abstract

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.