New super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with the P covered layer

Abstract

In order to design the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with low loss required for a power integrated circuit, a new super junction LDMOS with the P covered layer which is based on the existing N buffered super junction LDMOS is proposed in this paper for the first time. The key feature of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer, which is different from the N buffered super junction LDMOS. In this structure, the specific on-resistance of the device is reduced by using the high doped super junction layer; the problem of the substrate-assisted depletion which is produced due to the P-type substrate of the N-channel super junction LDMOS is eliminated by completely compensating for the charges of the N-type buffered layer and the P-type covered layer, thus improving the breakdown voltage. The charges of the N-type and P-type pillars are depleted completely. A new transmission path at the on-state is formed by N buffered layer to reduce the specific on-resistance, which is similar to the N buffered super junction LDMOS. However, the effect of N-type buffered layer of N buffered super junction LDMOS is not fully used. The drift region of the device is further optimized by the proposed device to reduce the specific on-resistance. The charge concentration of the N-type buffered layer in the proposed device is improved by the effect of charge compensation of the P covered layer. It is clear that high breakdown voltage and low specific on-resistance are realized in the proposed device by introducing the P-type covered layer and the N-type buffered layer. The results of the 3 D-ISE software suggest that when the drift region is on a scale of 10 μm, a specific on-resistance of 4.26 mΩ·cm2 obtained from P covered super junction LDMOS by introducing P covered layer and N buffered layer is reduced by about 59% compared with that of conventional super junction LDMOS which is 10.47 mΩ·cm2, and reduced by about 43% compared with that of N Buffered super junction LDMOS which is 7.46 mΩ·cm2.