Complete three-dimensional reduced surface field super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with semi-insulating poly silicon

Abstract

Lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is a key device for the power integrated circuit (PIC) and high voltage integrated circuit (HVIC) technologies. In order to break through the limit relation of 2.5 power between breakdown voltage (BV) and specific on-resistance (Ron,sp) for the traditional LDMOS, and improve the driving capability for the PIC by reducing the power consumption, the new SJ-LDMOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) is proposed in this paper for the first time, to the best of the authors' knowledge. In order to take full advantage of super junction concept, the SIPOS layer is used for SJ-LDMOS to achieve the effect of the complete three-dimensional reduced surface field (3D-RESURF) for the SJ-LDMOS. The substrate assisted depletion is effectively eliminated by the buffer layer under the super junction. The overall performances of the SIPOS SJ-LDMOS are improved by the uniform and high resistance of the SIPOS layer. The surface electric field is modulated to be uniform by the electric field modulation effect due to the SIPOS layer covering the field oxide. The higher BV would be achieved for the more uniform surface electric field because of the increased average lateral electric field. The BV for the unit length of the drift region is improved to 19.4 V/μupm. The SIPOS SJ-LDMOS along the 3D are subjected to the electric field modulation by the SIPOS layer, which achieves the complete 3D-RESURF effect, thus the drift region with the high concentration can be depleted completely to obtain the high BV. Moreover, in the on-state the majority carrier accumulation can be formed in the drift region of the SIPOS SJ-LDMOS due to the SIPOS layer, so that the specific on-resistance decreases further. In virtue of the ISE simulation, by optimizing the SIPOS layer of the proposed SIPOS SJ-LDMOS, the results show that the specific on-resistance of the SIPOS SJ-LDMOS is 20.87 mΩ·cm2 with a breakdown voltage of 388 V, which is less than 31.14 mΩ·cm2 for the N-buffer SJ-LDMOS with a breakdown voltage of 287 V, and far less than 71.82 mΩ·cm2 for the conventional SJ-LDMOS with a breakdown voltage of only 180 V with the same drift length.