Lateral Double-diffused MOSFET Research Articles

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.

New Strained LDMOS With Ultralow ON-Resistance by Si1−yCySource Stressor for About 20 V Low-Voltage Applications

A novel low ON-resistance strained lateral double-diffused MOSFET (LDMOS) with silicon-carbon (Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> ) source is proposed for low-voltage applications. Due to the lattice mismatch between silicon and Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> , the source-side Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1-y</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> stressor introduces the lateral tensile stress and vertical compressive stress along the conduction path to enhance the electron mobility in the channel and drift regions and hence improves the ON-state characteristics. As the stress relaxation in the drift region, the strain-induced breakdown voltage (BV) deterioration can be neglected. The simulation results show that the ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) of the proposed device is decreased by 19.2% compared with the conventional LDMOS without strain at a gate overdrive voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> -V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of 1 V. At the same time, the novel LDMOS achieves 47% and 28.8% increment in the drive current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D,sat</sub> ) and peak transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m,peak</sub> ), respectively, while keeping a nearly identical BV of 23.08 V. Besides, the improved cutoff frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and transconductance-to-current-ratio (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) are also obtained in the novel LDMOS.

Novel Lateral Double-Diffused MOSFET With Ultralow On-Resistance by the Variable Resistivity of Drift Region

In power devices, the resistance of the drift region is the main factor for determining the performance. To reduce the on-resistance, a novel lateral double-diffused MOSFET with variable resistivity of the drift region (VR LDMOS) is proposed in this letter. In the off state, the low doping concentration in the drift region is used to obtain high resistivity to support the reverse voltage. In the on state, the resistivity is significantly reduced by introducing electrons. This is different from the constant resistivity in the drift region of the conventional LDMOS. Ultralow on-resistance is obtained by the variable resistivity of the drift region. The simulation results show that the on-resistance is greatly reduced from 28.9m $\Omega \cdot $ cm2 of the conventional LDMOS to 1.5 $\text{m}\Omega \cdot $ cm2 of the VR LDMOS, which is almost 95% lower with the same 228 V breakdown voltage. Moreover, the current density is also been improved, which is 5 times higher than that of the conventional LDMOS.

Inserting Different Charge Regions in Power MOSFET for Achieving High Performance of the Electrical Parameters

In this paper a new lateral double diffused MOSFET is proposed which has better performance compared to the conventional MOSFET. The idea is applied by inserting two silicon windows in drift region near the drain and under this region. The window in the drift region has higher doping density that leads to reducing the on-resistance as an important parameter in LDMOSFETs. The silicon window in buried layer has higher thermal conductivity than insulator which leads to reducing the self heating effect. Moreover, inserting the windows leads to increasing the breakdown voltage. Improving the parameters in the proposed structure causes better drain current.

Novel Self-Modulated Lateral Superjunction Device Suppressing the Inherent 3-D JFET Effect

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance ${R} _{\text {on,sp}}$ especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage ${V} _{{\text {B}}}$ while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce ${R} _{\text {on,sp}}$ . Compared with the conventional SJ device, the measured ${V} _{\text {B}}$ of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with ${R} _{on,sp}$ reduced by 22.3% from 35.4 $\text{m}\Omega ~\cdot $ cm2 to 27.5 $\text{m}\Omega ~\cdot $ cm2.

The New Structure and Analytical Model of a High-Voltage Interconnection Shielding Structure With High-k Dielectric Pillar

The high-voltage interconnection (HVI) effect induces electric field crowding near the source region of power lateral double diffused metal oxide semiconductor field effect transistors (LDMOSs) and, therefore, weakens its breakdown voltage (BV) characteristic. To suppress such a detrimental effect, a novel HVI structure with a high- ${k}$ dielectric pillar beneath the HVI metal line is proposed. An analytical model is proposed to reveal the mechanism of the proposed structure and explain the effects of the parameters of the structure. The analytical model indicates that the high- ${k}$ dielectric pillar eliminates the electric field crowding near the source, promotes the depletion of the drift region, and avoids the premature breakdown. Meanwhile, due to the existence of the high- ${k}$ dielectric pillar, the surface electric field profile in the drift region can be modulated, and the influence of HVI can be effectively suppressed. Thus, a higher BV is obtained. The simulation results indicate that the proposed structure presents better BV, which is the same as that of the reduced surface field (RESURF) structure without HVI.

Experimental Study of 600 V Accumulation-Type Lateral Double-Diffused MOSFET With Ultra-Low On-Resistance

A novel Lateral Double-Diffused MOSFET (LDMOSFET) with ultra-low resistance is investigated by experiments. The proposed LDMOSFET features an extended gate field plate consisting of two back-to-back diodes. In the ON state, the electron accumulation layer is formed below the gate field plate and greatly reduces the resistance of the drift region. In the OFF state, the field plate assists in depleting the drift region and modulates the electric field distribution of the drift region, which ensures high breakdown voltage (BV). The key fabrication process steps for the proposed device are given. The fabricated prototype device shows specific on-resistance ( ${R} _{{\text {on},\text {sp}}}$ ) of 70 $\text{m}\Omega \cdot $ cm2 and BV of 680 V, which is superior performance for reported 600 V-rated lateral devices. The ${R} _{{\text {on},\text {sp}}}$ of the proposed LDMOSFET is decreased by 50% compared with the LDMOSFET without accumulation effect.

Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (R ON,sp ) of 28.53 mΩ·cm 2 , which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV 2 /R ON,sp of DG SJ-LDMOS is increased by 85.5 %.

The differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF LDMOSFETs

AbstractThe differences between N‐ and N+ buried layers in improving the breakdown voltage of RESURF (reduced surface field) LDMOSFETs (lateral double‐diffused metal‐oxide‐semiconductor field‐effect transistors) are discussed in this paper. Two concise RESURF criteria for LDMOS with a low‐doped fully depleted N‐ buried layer (NBL) and a highly doped nondepleted N+ floating layer (NFL) are developed by optimizing the lateral and vertical electric fields. The analytical solution quantitatively demonstrates the variation of the drift charge concentration and its dependence on the key NBL and NFL parameters. It also indicates that the NBL LDMOS achieves a superior tradeoff between specific on‐resistance (Rs,on)and breakdown voltage (BV) to the NFL LDMOS. The BV2/Rs,on for NBL LDMOS is 3.1 MW/cm2, which is increased respectively by 93.8% and 40.9% compared with the single RESURF and NFL‐LDMOS.

New Super-Junction LDMOS Breaking Silicon Limit by Multi-Ring Assisted Depletion Substrate

A novel super-junction (SJ) lateral double-diffused MOSFET with the multi-ring substrate (M-R SJ-LDMOS) is proposed for the first time. The substrate-assisted depletion (SAD) effect is eliminated by the n-type M-R to realize a balanced symmetric SJ with the low specific ON-resistance ( ${R}_{\text {on,sp}}$ ). Meanwhile, more uniform lateral and vertical electric field distributions are obtained under the surface and bulk electric field modulation effect, which leads to the enhancement of breakdown voltage (BV). The simulation results show that the BV of M-R SJ-LDMOS is increased by 427.2% and 81.2% in comparison with the conventional SJ-LDMOS and buffered step doping (BSD) SJ-LDMOS with the same drift region length, respectively. In addition, ${R}_{\text {on,sp}}$ of M-R SJ-LDMOS is reduced by 18.6% and 80.3% than that of BSD SJ-LDMOS and the conventional SJ-LDMOS. The figure-of-merit (FOM) of M-R SJ-LDMOS is 5.81 MW/cm2, which means the performance of M-R SJ-LDMOS is so excellent to break the silicon limit. +Moreover, the application of highly doped substrate ( ${3} \times {10}^{{15}}$ cm−3) in M-R SJ-LDMOS cuts the cost of substrate.

LDMOS with Variable-k Dielectric for Improved Breakdown Voltage and Specific On-resistance

A silicon-on-insulator (SOI) lateral doublediffused MOSFET (LDMOS) with variable-k dielectric is proposed, which features three-section high-k dielectrics placed over the drift region. Beneficial from the modulation, by high-k dielectrics, on electric fluxes in the drift region, the electric field strength is locally enhanced, and has a more uniform distribution along the surface of the drift region, which an increment of the breakdown voltage (BV) ascribes to. Moreover, due to the electric fluxes prefer to flow towards and through a high-k dielectric, an increase in the dose of the drift region is thus possible to reduce the specific on-resistance (R<SUB>on,sp</SUB>), since the extra electric fluxes caused by those increased impurities would flow, upwards, into the high-k dielectric, and barely make contributions to the xcomponent of the surface electric field, which indicates that the BV would not be affected. Based on a comparison with the conventional LDMOS, the BV of the proposed LDMOS increased by 31% with a decrease of 13% in the R<SUB>on,sp</SUB>. The figure of merit (FOM) increased approximately 2 times.

Numerical investigation on L-shaped vertical field plate in high-voltage LDMOS

In this work, an L-shaped vertical field plate (LVFP) is introduced in high-voltage lateral double-diffused MOSFET (LDMOS). The LVFP is embedded in an oxide trench that penetrates into the drift region. Compared with the conventional vertical field plate (VFP), the electric field surrounding the trench is enhanced for LVFP, and the depletion can penetrate deeper into the bulk silicon drift region. This improves the depletion of the drift region and thus the drift doping concentration (Nd). Consequently, the breakdown voltage (BV) increases while the on-resistance (Ron) decreases. The simulation results show that in comparison to the VFP device, the proposed device can achieve higher BV (=833 V) and lower Ron (=24.9 mΩ∙cm2).

A Novel High Voltage Ultra-Thin SOI-LDMOS With Sectional Linearly Doped Drift Region

A novel high voltage ultra-thin silicon on insulator (SOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) with a sectional linearly doped drift region is proposed and experimentally realized in this letter. The new device features a sectional linear doping (SLD) in a 0.17 μm SOI layer with a source field plate covering the full drift region. Low specific on-resistance Ron,sp is obtained by increasing the local doping concentration of the high resistance region. An analytical model is developed to provide the design guidance for the thin SOI devices with the field plate. The experimental results of the SOI SLD-LDMOS demonstrate that the new device shows a high breakdown voltage V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> of 960 V with a superior figure of merit (FOM = V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> / R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ) of 5.98 MW/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> when comparing with other reported thin SOI devices. Good agreements are observed between the model and the experimental results.

Potential of Utilizing High-$k$ Film to Improve the Cost Performance of Trench LDMOS

An idea of applying a film of high-k (HK) material to the trench lateral double-diffused MOSFET (LDMOS) is proposed and studied by simulation. Through introducing an HK film around the SiO2 trench, the flow of electric flux is guided, and the distribution of the surface electric field is modulated. As a result, the tradeoff relationship between breakdown voltage (BV) and specific $ \mathrm{\scriptscriptstyle ON}$ -resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ is improved. Simulation results indicate that the HK film with a permittivity of 475 and a thickness of 400 nm can effectively reduce ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ at the BV class of 200 V. Compared with the conventional device without HK, the proposed one is in a position to save about 60% of the chip area, while they are having the approximate performance and manufacturing complexity. Hence, the application of HK film is promising to improve the cost performance of trench LDMOS.

Research for radiation-hardened high-voltage SOI LDMOS

Based on the silicon-on-insulator (SOI) technology and radiation-hardened silicon gate (RSG) process, a radiation-hardened high-voltage lateral double-diffused MOSFET (LDMOS) device is presented in this paper. With the gate supply voltage of 30 V, the LDMOS device has a gate oxide thickness of 120 nm, and the RSG process is effective in reducing the total ionizing dose (TID) radiation-induced threshold voltage shift. The p-type ion implantation process and gate-enclosed layout topology are used to prevent radiation-induced leakage current through a parasitic path under the bird's beak and at the deep trench corner, and the device is compatible with high-voltage SOI CMOS process. In the proposed LDMOS, the total ionizing dose radiation degradation for the ON bias is more sensitive than the OFF bias. The experiment results show that the SOI LDMOS has a negative threshold voltage shift of 1.12 V, breakdown voltage of 135 V, and off-state leakage current of 0.92 pA/μm at an accumulated dose level of 100 krad (Si).

PSJ LDMOS with a VK dielectric layer

A partial super junction lateral double-diffused metal–oxide–semiconductor field-effect transistor with a variable- k dielectric layer (PSJ VK LDMOS) is proposed in this Letter. Low- k material and PSJ are introduced into the device. PSJ provides a low-resistance channel to reduce the specific on-resistance ( R on,sp ). Furthermore, according to an enhanced dielectric layer field, low- k buried layer can sustain the high breakdown voltage (BV). To eliminate substrate-assisted depletion effect and improve the lateral BV of the proposed structure, the charge compensation layer in the device adopts a variation of lateral doping technique and is combined with the N pillar in PSJ. Ultimately, the simulation results show that BV of 795.5 V and the figure of merit (FOM) of 6.1 MW cm −2 are achieved for PSJ VK LDMOS. BV and FOM are enhanced by 71.4 and 81.1%, respectively, compared with con. PSJ SOI LDMOS with the drift region length of 46.5 μm. Furthermore, R on,sp of 103.4 mΩ cm 2 is reduced by 31.2% compared with the ‘silicon limit’ at the same BV class, which breaks the ‘silicon limit’.

Novel Superjunction LDMOS With a High-K Dielectric Trench by TCAD Simulation Study

A novel superjunction (SJ) lateral double-diffused MOSFET (LDMOS) with a deep High-K(HK) dielectric trench (HK SJ-LDMOS) is proposed and its mechanism is investigated by Technology Computer Aided Design (TCAD) simulations. The HK dielectric trench is embedded under the n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drain, which is connected with the drain electrode. In the OFF-state, the reshaping effect of HK trench enhances the bulk electric field strength and weakens the peak electric field around the edge of the drain diffusion, which increases the breakdown voltage (BV). Moreover, because of the assistant depletion effect by the HK trench, a lower resistivity substrate is allowed for HK SJ-LDMOS, which also increases the doping concentration of the ntype buffer layer under the SJ layer of HK SJ-LDMOS, correspondingly. Thus, a lower specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) is also obtained. Simulation results show that the BV increases by 35.2% in comparison with the conventional buffered SJ-LDMOS with the same drift length. Moreover, HK SJ-LDMOS presents an excellent figure of merit, which is two times higher than that of the conventional buffered SJ-LDMOS.

Stacked lateral double-diffused metal-oxide-semiconductor field effect transistor with enhanced depletion effect by surface substrate**Project supported by the National Natural Science Foundation of China (Grant No. 61464003) and the Guangxi Natural Science Foundation, China (Grant Nos. 2015GXNSFAA139300 and 2018JJA170010).

A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) with enhanced depletion effect by surface substrate is proposed (ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches (SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance (Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage (BV). Compared to a conventional LDMOS (C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 mΩ·cm2 to 23.24 mΩ·cm2 and the Baliga’s figure of merit (FOM) of is 9.07 MW/cm2.

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance. The realization of RFP barely complicates the device fabrication, but it motivates QVSJ to significantly improve the relationship between breakdown voltage (BV) and specific on-state resistance ( ${R} _{\mathrm{ON,SP}}$ ). The simulation results show that compared with the conventional QVSJ T-LDMOS, the proposed one gains the ${R} _{\mathrm{ON,SP}}$ reduced by about 79% under the same BV requirement of about 500 V. It therefore presents an excellent figure of merit (FOM) (FOM = BV2/ ${R} _{\mathrm{ON,SP}}$ , Baliga’s FOM) up to 29.8 MW/cm2, which is superior to the prior art and exhibits a bright prospect of saving energy.

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

A silicon-on-insulator (SOI) p-channel lateral double-diffused MOSFET (p-LDMOS), conducting not only holes but also electrons, is proposed and investigated by TCAD simulations. Its most important advantage is the greatly improved relationship between the breakdown voltage (BV) and the specific on-resistance ( ${R} _{\mathrm{ on,sp}}$ ). The improvement is mainly attributed to two aspects. First, many holes can accumulate in the p-drift region in the on-state, which provides a low-resistance path for hole conduction. Second, a paralleled n-LDMOS is, meanwhile, automatically triggered to form a new path for electrons. Electrons have higher mobility than holes; thus, the device performance is further improved. Based on a simulation comparison with the previous p-LDMOS at the same BV of 300 V, the ${R} _{\mathrm{ on,sp}}$ of the proposed p-LDMOS decreased by 78% and the figure of merit (FOM) increased approximately 3.4 times. Moreover, the proposed device still has the conventional three-terminal style, and its fabrication process is compatible with CMOS technology.