Superjunction LDMOS With Dual Gate for Low On-Resistance and High Transconductance

Zhen Cao,Licheng Jiao

doi:10.1109/jeds.2020.3011929

Abstract

In this paper, a novel bulk silicon lateral superjunction double diffused MOSFET (SJ-LDMOS) with dual gate (DG) is proposed and its mechanism is investigated by numerical TCAD simulations. The proposed structure features the combination of a trench gate and a planar gate, forming two current conduction paths. One current conduction takes place along the highly doped N-pillar. The other is through the N-buffer layer ensuring uniform current distributions, which solves the problem of low conduction in the N-buffer layer of the SJ-LDMOS structures. The dual conduction paths improve the current uniformity through the entire SJ layer and the N-buffer layer, which effectively reduces the resistance of the device. Simulation results indicate that the proposed device is predicted to achieve a high breakdown voltage (BV) of 643 V and an extremely low specific ON-resistance (R ON,sp ) of 28.53 mΩ·cm 2 , which is by 46.7 % lower than that of the previously N-buffer SJ-LDMOS structures with the same drift length. Besides, the transconductance of DG SJ-LDMOS is increased by 54.5 % and the figure of merit (FOM) on BV 2 /R ON,sp of DG SJ-LDMOS is increased by 85.5 %.

Highlights

Superjunction (SJ) technology is with the ability to achieve a remarkable low specific ON-resistance (RON,sp) at a given breakdown voltage (BV) while keeping almost all of the advantages of the power MOSFET, which has been realized in the 500–900 V power SJ MOSFET [1]–[4]
In order to further reduce the resistance of the LDMOS, several types of trench LDMOS have been reported to improve the performance of the conventional LDMOS [18]–[24], these structures are mainly adopted for the low voltage applications
In this paper, to illustrate the credibility of the simulation, the TCAD simulation [26] is calibrated to experimental breakdown characteristics (Ids − Vds) data extracted from N-Buffer SJ-LDMOS [8] and Triple RESURF (Reduced SURface Field) LDMOS [27] with a certain channel width (WCh) shown in Fig. 2 (a)

Summary

Introduction

Superjunction (SJ) technology is with the ability to achieve a remarkable low specific ON-resistance (RON,sp) at a given breakdown voltage (BV) while keeping almost all of the advantages of the power MOSFET, which has been realized in the 500–900 V power SJ MOSFET [1]–[4]. N-buffer SJ-LDMOS structures is still limited at high voltage ratings (∼600V).This is because of the JFET effect of N/P pillars.

Results

Conclusion