High voltage SOI SJ-LDMOS on composite substrate

Abstract

A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted depletion (SAD) effect. In addition, the N-buffer layer increases the vertical breakdown voltage without increasing the thickness of BOX. The proposed device preserves the isolation advantage of SOI device because the N-buffer layer is self-isolation. Numerical simulation results indicate that a breakdown voltage of 280 V for the proposed device with drift length of 15 mum, comparing with a breakdown voltage of 150 V for conventional SOI SJ-LDMOS suffering for the SAD effect.