Lateral Double-diffused MOSFET Research Articles

New technique to extend the vertical depletion region at SOI-LDMOSFETs

In order to obtain an excellent performance for silicon-on-insulator lateral double-diffused MOSFET (SOI-LDMOSFET) transistors, we introduce a new technique to extend the depletion region along the vertical direction in the drift region. The proposed structure is called vertically depleted LDMOSFET (VD-LDMOSFET). The VD-LDMOSFET structure consists of a buried metal layer in the oxide region. The drift region of the VD-LDMOSFET is vertically depleted, not only from the buried oxide, but also by the incorporated metal layer in the buried oxide. Therefore, a higher drift doping density is achieved by an extension of the depletion region in the drift region and the on-state resistance $$({R}_{\mathrm{ON}})$$ reduces without degradation of the breakdown voltage. Also, an additional peak is created in the electric field distribution of the proposed structure and causes a reduction of the electric field peak near the gate and the drift region junction at the top surface of the device. Therefore, the breakdown voltage $$({V}_{\mathrm{BR}})$$ of the VD-LDMOSFET structure increases. The simulation results illustrate that by optimizing the doping density of the drift region and the dimensions of the metal layer in the proposed structure, the on-state resistance (28.9%) and the breakdown voltage (36.1%) are improved greatly and a superior tradeoff is achieved compared with a conventional SOI-LDMOSFET (C-LDMOSFET) structure.

Dimension Effect on Breakdown Voltage of Partial SOI LDMOS

Dimension effect on breakdown voltage (BV) of lateral double-diffused metal-oxide–semiconductor field-effect transistor in partial silicon-on-insulator (PSOI) technology is comprehensively studied. The maximum BV (BVmax) is examined under various settings of the device length ${L}$ and the active silicon film thickness ${t}$ . It is shown that there exists an optimal pair of ( ${L}$ , ${t}$ ) for PSOI at which the highest BV can be achieved. The ratio of ${L}$ / ${t}$ is better chosen between 5 and 7 for the device designs, in particular, $L/t={\mathrm{ 6}}$ can be considered as the optimal one theoretically. Moreover, impacts of the silicon window length $L_{w}$ and the drift doping concentration $N_{dr}$ on the BV, the on-resistance ( $R_{\mathrm{ on}}$ ) and the figure-of-merit ( $=\!{\mathrm{ BV}}^{2}/R_{\mathrm{ on}}$ ) are also carefully studied.

Novel lateral double-diffused MOSFET with vertical assisted deplete-substrate layer

Lateral double-diffused MOSFETs (LDMOS) are widely used in high voltage integrate circuits and smart power integrate circuits because of their lateral channels and their electrodes located on the surface of the device, thereby facilitating integration with other low-voltage circuits and devices, and they have become the core technology of the second electronic revolution. In order to optimize the breakdown characteristics and the performance of the LDMOS, in this paper, a novel LDMOS is proposed with the vertical assisted deplete-substrate layer (ADSL) on the basis of traditional LDMOS structure. The new ADSL layer makes the vertical depletion region below the drain expand to substrate excessively, thus introduces a new electric field peak at the bottom of the ADSL layer by using the electric field modulation effect, so that the vertical electric field is optimized. The ISE simulation results show that when the lengths of the drift region of ADSL LDMOS and traditional LDMOS are both 70 m, the breakdown voltage is increased from 462 V to 897 V, improved by about 94%. Also, the figure-of-merit (FOM) is upgraded from 0.55 MW/cm2 to 1.24 MW/cm2, increased by 125%. Therefore, the new structure ADSL LDMOS has a great improvement in device performance compared with that of the traditional LDMOS. Moreover, authors have studied the ADSL LDMOS from three parts, all of these confirm that the new structure has a great potential application in power device. Firstly, through the lateral surface electric field distributions and vertical electric filed distributions of conventional LDMOS and ADSL LDMOS, a new electric field peak at the bottom of the ADSL is introduced in the vertical direction. Secondly, the mechanism for the new structure can present a deeper understanding through the ADSL LDMOS concentration and structural parameter optimization process. The FOM is optimized when the drift region concentration and ADSL concentration are 1.81015 cm-3 and 6.51015 cm-3, respectively, and it can reach a best value when the ADSL length is 40 m. Thirdly, the ADSL layer is further partitioned and optimized. On the basis of the new structure, the breakdown voltage is increased to 938 V when the new structure is based on the dual partition, and in the triple partition the breakdown voltage reaches 947 V. In this paper, through simulations, the detailed analyses of the proposed new structure of the mechanism and its performance are conducted, and the breaking of the breakdown characteristics of silicon-based devices is of special significance for developing the lateral power devices.

Optimization and New Structure of Superjunction With Isolator Layer

An optimization theory is developed for the balanced symmetric superjunction with the interface isolator layer (I-SJ) in this paper. The theory includes two parts: the electric field calculation by the Taylor series method; the design formulas by the minimum specific on-resistance $R_{\mathrm{\scriptscriptstyle ON},\mathrm {min}}$ optimization. Based on the theory, a new I-SJ structure with a single cell is proposed, which shows the minimum $R_{{\mathrm{\scriptscriptstyle ON}}}$ among the superjunction (SJ) devices with the $1~\mu \text{m}$ shallow depths. $R_{\mathrm{\scriptscriptstyle ON}}$ of the new device is reduced by 53.5% compared with that of the conventional SJ lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) and 67.6% with the conventional LDMOS under the same breakdown voltage $V_{B}$ of 658 V.

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET**Project supported by the National Natural Science Foundation of China (Grant No. 61306094), the Project of Hunan Provincial Education Department, China (Grant No.13ZA0089), the Introduction of Talents Project of Changsha University of Science & Technology, China (Grant No. 1198023), and the Construct Program of the Key Discipline in Hunan Province,

A novel voltage-withstand substrate with high-K (HK, k > 3.9, k is the relative permittivity) dielectric and low specific on-resistance (Ron,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS)is proposed in this paper. The high-K dielectric and highly doped interface N+-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (Nd) and reshape the electric field distribution. The highly doped N+-layer under the high-K dielectric acts as a low resistance path to reduce the Ron,sp. The new device with the high breakdown voltage (BV), the low Ron,sp, and the excellent figure of merit (FOM = BV2/Ron,sp) is obtained. The BV of HKLR LDMOS is 534 V, Ron,sp is 70.6 mΩ·cm2, and FOM is 4.039 MW·cm−2.

A Fast Switching Current Regulator Using Slewing Time Reduction Method for High Dimming Ratio of LED Backlight Drivers

This brief proposes a fast switching current regulator to achieve a high dimming ratio of the light-emitting diode (LED) backlight drivers. The proposed current regulator employs the slewing time reduction method to enhance the dimming ratio by decreasing the rising time of the LED forward current. A six-channel LED backlight driver was fabricated using a 0.35- $\mu\text{m}$ bipolar-CMOS-DMOS process technology which includes an n-type MOSFET with a low voltage of 5 V and a high-side lateral double diffused MOSFET with a breakdown voltage of 60 V. The measured rising time and minimum pulsewidth of the LED forward current are reduced to 4.8 ns and 12 ns, respectively, at a current transition of 60 mA. Consequently, the dimming ratio of the LED backlight driver using the proposed current regulator is calculated to be 160 000 : 1 at a dimming frequency of 500 Hz, which is more than three times higher than that obtained using the previously reported current regulators. Therefore, the proposed current regulator is suitable for high-end displays which require high image quality.

Ultralow ON-Resistance High-Voltage p-Channel LDMOS With an Accumulation-Effect Extended Gate

The high ON-resistance and the limited breakdown voltage (BV) are the two major issues for the p-channel lateral double-diffused MOSFET (pLDMOS). To solve the two issues, an ultralow specific ON-resistance ( $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ ) pLDMOS with improved BV is proposed and investigated by simulation. It features an extended gate (EG) with accumulation effect over the drift region and a P+ floating layer (PFL) in the N-sub. In the ON-state, the EG induces the hole accumulation layer along the drift region surface, providing an ultralow-resistance conducting path. This accumulation-type current transport mode makes $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ almost independent of the drift region doping concentration ( $N_{d}$ ) and contributes to a much lower $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ , which greatly breaks through the silicon limit of $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}\propto \textrm {BV}^{2.5}$ . In the OFF-state, the EG not only modulates the surface electric field ( $E$ -field) distribution to enhance the BV, but also helps deplete the drift region to increase the optimized $N_{d}$ , and thus further reduce $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ . Moreover, the PFL is not depleted, and thus equipotential in the lateral direction. Therefore, the PFL not only modulates the bulk $E$ -field distribution at the source and drain sides but also introduces an additional vertical diode to sustain a higher BV. Owing to the effects mentioned above, the simulated results show that the EG PFL pLDMOS decreases $R_{\mathrm{\scriptscriptstyle ON},\textrm {sp}}$ by 68% and increases the BV by 47% compared with the conventional pLDMOS.

A High-Voltage (>600 V) N-Island LDMOS With Step-Doped Drift Region in Partial SOI Technology

A high-voltage lateral double-diffused MOSFET with N-island (NIS) and step-doped drift (SDD) region in partial silicon-on-insulator (PSOI) technology is proposed. In the lateral direction, the SDD region and the NIS on the buried oxide layer (BOX) introduce two additional electric field peaks, which can improve the surface field distribution and breakdown voltage (BV). In the vertical direction, due to the highly doped NIS, a higher electric field is induced into the BOX layer, which can achieve a higher vertical BV. As a consequence, the BV is enhanced significantly. Moreover, the NIS with a larger doping concentration can provide a higher current of the proposed device, and thus, the ON-resistance ( $R_{{\mathrm{\scriptscriptstyle ON}}})$ is reduced. The 2-D simulation results show that the BV of the proposed structure can achieve 680 V, and $R_{{\mathrm{\scriptscriptstyle ON}}}$ is reduced by 10.2% and 14.7% in comparison with the conventional PSOI and buried n-type layer PSOI, respectively.

Design of a novel triple reduced surface field LDMOS with partial linear variable doping n-type top layer

A novel triple reduced surface field (RESURF) lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS) with partial linear variable doping (LVD) N-type top (N-top) layer is proposed in this paper. Compared with the conventional triple RESURF LDMOS, a partial LVD N-top layer is introduced in the surface of N-well, providing a low on-resistance conduction path and leading to an optimized surface electric field, which alleviates the inherent tradeoff between the breakdown voltage (BV) and specific on-resistance (Ron,sp). With the n-drift region length of 70 μm, the novel triple RESURF LDMOS obtains a high BV of 847 V and a low Ron,sp of 79 mΩ cm2 which are 76 V higher and 46 mΩ cm2 lower than those of the conventional triple RESURF LDMOS. Therefore, the novel triple RESURF LDMOS can greatly improve the tradeoff between BV and Ron,sp. Furthermore, compared with the other existing technologies in the high BV level, the novel triple RESURF LDMOS can achieve a highest figure of merit (FOM, defined as BV2/Ron,sp) of 9.08 MW/cm2 and the conventional RESURF silicon limits are broken.

Modeling of a triple reduced surface field silicon-on-insulator lateral double-diffused metal–oxide–semiconductor field-effect transistor with low on-state resistance**Project supported by the National Natural Science Foundation of China (Grant No. 61376080), the Natural Science Foundation of Guangdong Province, China (Grant No. 2014A030313736), and the Fundamental Research Funds for the Central Universities, China (Grant No. ZYGX2013J030).

An analytical model for a novel triple reduced surface field (RESURF) silicon-on-insulator (SOI) lateral double-diffused metal–oxide–semiconductor (LDMOS) field effect transistor with n-type top (N-top) layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional (2D) Poisson’s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage (BV) is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer (Qntop) is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results, showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.

A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region

Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region.

Design of a 700 V DB-nLDMOS Based on Substrate Termination Technology

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of $\Delta L_{1,}\Delta L_{2,}$ and $\Delta L_{3}$ which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}}$ of 105.6 $\text{m}\Omega \cdot {\mathrm{ cm}}^{2}$ based on $L_{d}$ and high BV of 788 V are achieved by the DB-nLDMOS.

Trench-gate-integrated superjunction lateral double-diffused MOSFET with low specific on-resistance

In this paper, a new low-voltage planar gate superjunction (SJ) lateral double-diffused MOSFET (LDMOSFET) is presented. The proposed trench-gate-integrated SJ-LDMOSFET is composed of a conventional planar gate structure and a trench gate structure extending into a drift region through a channel region, which helps reduce both drift resistance and channel resistance. By device simulation, we confirmed that current crowding near the top surface was alleviated by the spread of electron current into the drift region through the accumulation layer of the trench gate. As a result, the specific on-resistance (RON · A) of the trench-gate-integrated SJ-LDMOSFET can be reduced by increasing SJ thickness (TSJ), and the trench-gate-integrated SJ-LDMOSFET with a TSJ of 4 µm achieved an RON · A of 0.47 mΩ·cm2 at a breakdown voltage of 97 V. This is about 14% lower than the one-dimensional Si limit.

A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs.Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100μA), at drain–source voltage of VDS=100V and gate–source voltage of VGS=25V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87μA and 51μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

A New Solution for Superjunction Lateral Double Diffused MOSFET by Using Deep Drain Diffusion and Field Plates

A new solution based on the concept of a deep drain diffusion combined with field plates (FPs) is proposed for the superjunction lateral double diffused MOSFET (SJ-LDMOS) device. The deep drain diffusion suppresses the curvature effect of the conventional SJ-LDMOS and the FPs optimize the electric field distribution further. Simulated results show that the proposed SJ-LDMOS exhibits figure of merits of 12.8 and 8.5 MW/cm $^{\mathrm{{2}}}$ for 700 and 1200 V ratings, respectively, which are about 20% better than the prior art. Moreover, the proposed SJ-LDMOS is less sensitive to the charge imbalance. Using the isotropic etch technique followed by implantation, the deep drain diffusion is easy to be fabricated.

New super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with the P covered layer

In order to design the lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) with low loss required for a power integrated circuit, a new super junction LDMOS with the P covered layer which is based on the existing N buffered super junction LDMOS is proposed in this paper for the first time. The key feature of the proposed structure is that the P-type covered layer is partly above the N-type of the super junction layer, which is different from the N buffered super junction LDMOS. In this structure, the specific on-resistance of the device is reduced by using the high doped super junction layer; the problem of the substrate-assisted depletion which is produced due to the P-type substrate of the N-channel super junction LDMOS is eliminated by completely compensating for the charges of the N-type buffered layer and the P-type covered layer, thus improving the breakdown voltage. The charges of the N-type and P-type pillars are depleted completely. A new transmission path at the on-state is formed by N buffered layer to reduce the specific on-resistance, which is similar to the N buffered super junction LDMOS. However, the effect of N-type buffered layer of N buffered super junction LDMOS is not fully used. The drift region of the device is further optimized by the proposed device to reduce the specific on-resistance. The charge concentration of the N-type buffered layer in the proposed device is improved by the effect of charge compensation of the P covered layer. It is clear that high breakdown voltage and low specific on-resistance are realized in the proposed device by introducing the P-type covered layer and the N-type buffered layer. The results of the 3 D-ISE software suggest that when the drift region is on a scale of 10 μm, a specific on-resistance of 4.26 mΩ·cm2 obtained from P covered super junction LDMOS by introducing P covered layer and N buffered layer is reduced by about 59% compared with that of conventional super junction LDMOS which is 10.47 mΩ·cm2, and reduced by about 43% compared with that of N Buffered super junction LDMOS which is 7.46 mΩ·cm2.

Complete three-dimensional reduced surface field super junction lateral double-diffused metal-oxide-semiconductor field-effect transistor with semi-insulating poly silicon

Lateral double-diffused metal-oxide-semiconductor field-effect transistor (LDMOS) is a key device for the power integrated circuit (PIC) and high voltage integrated circuit (HVIC) technologies. In order to break through the limit relation of 2.5 power between breakdown voltage (BV) and specific on-resistance (Ron,sp) for the traditional LDMOS, and improve the driving capability for the PIC by reducing the power consumption, the new SJ-LDMOS with the semi-insulating poly silicon (SIPOS SJ-LDMOS) is proposed in this paper for the first time, to the best of the authors' knowledge. In order to take full advantage of super junction concept, the SIPOS layer is used for SJ-LDMOS to achieve the effect of the complete three-dimensional reduced surface field (3D-RESURF) for the SJ-LDMOS. The substrate assisted depletion is effectively eliminated by the buffer layer under the super junction. The overall performances of the SIPOS SJ-LDMOS are improved by the uniform and high resistance of the SIPOS layer. The surface electric field is modulated to be uniform by the electric field modulation effect due to the SIPOS layer covering the field oxide. The higher BV would be achieved for the more uniform surface electric field because of the increased average lateral electric field. The BV for the unit length of the drift region is improved to 19.4 V/μupm. The SIPOS SJ-LDMOS along the 3D are subjected to the electric field modulation by the SIPOS layer, which achieves the complete 3D-RESURF effect, thus the drift region with the high concentration can be depleted completely to obtain the high BV. Moreover, in the on-state the majority carrier accumulation can be formed in the drift region of the SIPOS SJ-LDMOS due to the SIPOS layer, so that the specific on-resistance decreases further. In virtue of the ISE simulation, by optimizing the SIPOS layer of the proposed SIPOS SJ-LDMOS, the results show that the specific on-resistance of the SIPOS SJ-LDMOS is 20.87 mΩ·cm2 with a breakdown voltage of 388 V, which is less than 31.14 mΩ·cm2 for the N-buffer SJ-LDMOS with a breakdown voltage of 287 V, and far less than 71.82 mΩ·cm2 for the conventional SJ-LDMOS with a breakdown voltage of only 180 V with the same drift length.

A new high-side and low-side LDMOST with a selective buried layer in the substrate

In this article, a novel low- and high-side lateral double-diffused metal–oxide–semiconductor field-effect-transistor (LDMOST) with an n-type selective buried layer (SBL-LDMOST) in a p-type substrate is presented. When the device operates in the high-side mode, the buried layer prevents vertical punch-through and then the vertical breakdown voltage (BV) is enhanced. When the device operates in the low-side mode, the depleted space-charges in the selective buried layer modulate the bulk electric field and then enhance the substrate to sustain higher reverse voltage. Simulation results show that the low-side BV increases from 585V of the conventional LDMOST to 688V and the high-side BV increases from 962V to 1791V at the same 60μm drift region lengths condition. In addition, when operating in the high-side mode, the drive-current is not alleviated due to drift region immunity from depletion.

Electric field optimized LDMOST using multiple decrescent and reverse charge regions

A lateral double-diffused metal—oxide—semiconductor field effect transistor (LDMOST) with multiple n-regions in the p-substrate is investigated in detail. Because of the decrescent n-regions, the electric field distribution is higher and more uniform, and the breakdown voltage of the new structure is increased by 95%, in comparison with that of a conventional counterpart without substrate n-regions. Based on the trade-off between the breakdown voltage and the on-resistance, the optimal number of n-regions and the other key parameters are achieved. Furthermore, sensitivity research shows that the breakdown voltage is relatively sensitive to the drift region doping and the n-regions' lengths.

Low specific on-resistance power MOSFET with a surface improved super-junction layer

A novel low specific on-resistance (Ron,sp) integrable power metal-oxide-semiconductor field-effect transistor (MOSFET) with a surface improved super-junction (SISJ) layer is proposed. A super-junction layer is implemented at the surface of the drift region and the P pillar in super-junction layer is split into two parts with different doping concentrations. Firstly, the super-junction layer causes the multiple-direction depletion effect. The drift region doping concentration of the SISJ LDMOS is therefore increased significantly. Secondly, the super-junction layer provides a surface low on-resistance path. Thirdly, the new electric field peak introduced by the variation in the doping concentration of the P pillar modulates the surface electric field distribution, resulting in an improved breakdown voltage (BV). It reduces the device pitch for a specific BV capacity. All of them decrease Ron,sp sharply. The SISJ LDMOS exhibits a Ron,sp of 10.2mΩcm2 for BV=230V and decreases Ron,sp by 37% compared with a conventional lateral double-diffused MOSFET (LDMOS) at the same BV. Finally, because of the shallow depth of the SISJ layer, the proposed structure can be compatible with CMOS technology. Consequently, the SISJ LDMOS must be a competitive power device for power integrated circuit applications.