Lateral Double-diffused MOSFET Research Articles

A novel double-gate trench SOI LDMOS with double-dielectric material by TCAD simulation study

In this paper, a novel double-gate trench silicon-on-insulator lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with double-dielectric material (DGDK-LDMOS) is proposed. DGDK-LDMOS has two dielectric materials: a reverse-L-shaped high-k (HK) thin film and an low-k (LK) buried oxide layer. The HK thin film optimizes the electric field distribution on the drift region surface, attracting electric flux, and the excellent withstand voltage of the LK buried oxide layer can significantly improve the breakdown voltage (BV) and reduce specific on-resistance (R on,sp) of the device. The modulation mechanism of LDMOS by HK thin film and LK buried oxide layer is analyzed. The results show that compared with conventional LDMOS, when the permittivity of HK thin film is 25 and the permittivity of LK buried oxide is 3, the BV of DGDK-LDMOS is increased by 89.6%, the R on,sp is decreased by 26.4%, and the figure of merit (FOM, FOM = BV2/R on,sp) is increased by 397.2% from 3.6 MW cm−2 to 17.9 MW cm−2. Meanwhile, the output characteristics, transfer characteristics, lattice temperature, AC characteristics and switching characteristics of DGDK-LDMOS are also discussed and compared.

Temperature Reliability Investigation for a 400 W Solid-State Power Amplifier under High and Cold Conditions

In order to study the temperature reliability of high-power amplifiers under high cand cold conditions, a 400 W solid-state power amplifier was taken as an example to explore the variation in its performance. The test results showed that its output power, gain, and power-added efficiency increased with the increase in temperature at a fixed frequency. Under a fixed input power, Pout and gain both showed different trends with the rising temperature. Within the frequency band of 2–10 MHz, the higher the temperature, the better the output power and gain. However, within the frequency range of 10–30 MHz, the higher the temperature, the worse the performance. Moreover, with the increasing temperature, its power-added efficiency, the second harmonic and the third harmonic also showed a decreasing trend. Detailed analysis showed that the degradation and inversion of performance parameters are closely related to the zero temperature coefficient and self-heating effect of the lateral double-diffused metal–oxide–semiconductor field-effect transistor. Meanwhile, it is also affected by the circuit structure and thermal design of the PA. In order to ensure stable performance in different environments, performance degradation can be improved by hardware compensation. Therefore, analyzing the working parameters at different temperatures for high-power PAs is the key to achieving temperature control and ensuring their long-term stability and reliability. This can provide relatively accurate reference data for subsequent heat dissipation optimization, greatly improve design efficiency, and even shorten the development cycle and reduce costs.

Study of ultra-low specific on-resistance and high breakdown voltage SOI LDMOS based on electron accumulation effect

A novel stepped L-shaped trench gate silicon-on-insulator (SOI) lateral double-diffused metal oxide semiconductor field-effect transistor (LDMOS) with N-pillar (SLTGN-LDMOS) is proposed. SLTGN-LDMOS contains a highly doped N-pillar, assisting in reducing the specific on-resistance (R on,sp). The stepped L-shaped trench gate (SLTG) attracts electrons to attach to the edge of the trench, thus directing more current to flow along the edge, which decreases R on,sp effectively. Furthermore, new electric field peaks are generated on the surface of the drift region, thus increasing the breakdown voltage (BV). As a result, compared with the conventional structure (C-LDMOS), the BV of SLTGN-LDMOS increases from 63 V to 162.7 V, and the R on,sp decreases from 1.85 mΩ·cm2 to 1.46 mΩ·cm2. Then, the figure of merit (FOM1, BV2 /R on.sp) increases remarkably from 2.15 MW·cm−2 to 18.13 MW·cm−2. In addition, the maximum surface temperature of SLTGN-LDMOS is 395.3 K, slightly lower than the 398.7 K of C-LDMOS.

A novel high-performance trench lateral double-diffused MOSFET with buried oxide bump layer

A shallow-trenched Lateral Double-Diffused MOSFET with folded drift region (FD LDMOS) is proposed in this paper. The new structure divides the drift region into two parts. The left side is introduced in a shallow trench, and the right side is used to take advantage of the buried oxide bump layer. The new structure optimizes the lateral and vertical electric fields simultaneously. The self-adaptation of the drift region improves the doping concentration (Ndd), reducing specific on-resistance (Ron,sp) and parasitic capacitance. The simulation results show that compared with the conventional LDMOS (Con. LDMOS), the breakdown voltage (BV) has increased by 53%, and the figure of merit (FOM) has increased by 173.4%; the power-added efficiency (PAE) near the P3dB operating point is increased from 44.43% to 63.67% at the frequency of 1.2 GHz.

TID Effect of MOSFETs in SOI BCD Process and Its Hardening Technique

The TID effect of low operation voltage MOSFET (LV-MOS), medium operation voltage lateral double-diffused MOSFET (MV-LDMOS), and 600V high operation voltage LDMOS (HV-LDMOS) manufactured by SOI BCD process is investigated by experiments and 3D TCAD numerical simulations and the hardening technique is proposed and discussed. The experiment and simulation results of LV-MOS with three different structures indicate that the TID-induced leakage current is mainly caused by the STI oxide, which forms a leakage current path along the side of channel region. The leakage current of LV-MOS with a square/ring shape gate structure does not increase even though the irradiation dose increases to 300 krad(Si). The square/ring shape gate structure can eliminate the TID-induced leakage current induced by segregating the channel from STI region, which is used in MV-LDMOS and 600V HV-LDMOS. The TID-induced leakage current of radiation-hardened MV-LDMOS does not increase at the irradiation dose of 300 krad(Si). The TID-induced leakage current of radiation-hardened 600V HV-LDMOS is about four orders of magnitude less than that of standard 600V HV-LDMOS at the irradiation dose of 50 krad(Si). The specific-on-resistance performance of MV-LDMOS and 600V HV-LDMOS is improved with the increase of irradiation dose. The radiation-hardened technique used in this paper can improve the TID tolerance of MOSFETs in SOI BCD process significantly. The systematic and thorough investigation of TID hardening technique of SOI BCD technology will contribute to the application of power ICs in space environment.

Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region Achieving Ultralow Specific ON Resistance

In order to reduce the specific ON resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ </tex-math></inline-formula> ) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> . Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> of the FALDMOS is only 9.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm2, while that the conventional LDMOS is 36.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.

Single-event burnout of LDMOS with polygon P+ structure

The performance and triggering mechanism of the single-event burnout (SEB) of the lateral double diffused MOSFET with polygon P+ insert structure (PP-LDMOS) are evaluated by 2-D numerical simulations. The novel PP-LDMOS and the conventional LDMOS are analyzed and compared to examine the effect of the polygon P+ insert structure on the SEB performance of the LDMOS device. The most sensitive volume of the conventional LDMOS and PP-LDMOS are investigated. In addition, the hardening mechanism of PP-LDMOS is explained. The simulation results show that the polygon P+ structure can discharge the holes generated by the ion's strike effectively. Compared with the conventional LDMOS structure, the polygon P+ insert structure can improve the SEB threshold voltage from 19 % to 88 % of breakdown voltage.

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

Super Junction Lateral Double-Diffused MOSFET with Ultra-low Specific on-Resistance Completely Eliminating Substrate Assisted Depletion Effect

A novel LDMOS with optimized electric field distribution to eliminate substrate assisted depletion effect

A novel N-channel Super Junction Lateral double-diffused MOSFET (SJ LDMOS) with optimized electric field distribution is proposed. To eliminate substrate assisted depletion (SAD) effect, the source-drain electrodes of the proposed device are used to form a voltage in the substrate equal to the SJ layer. Then the surface of the substrate is depleted through the buffer layer. The substrate and the SJ layer are independently depleted, and form a similar electric field distribution. The influence of the substrate on the SJ layer is greatly removed. Finally, the influence of the substrate on SJ layer is completely eliminated. Under the same drift length of 20 μm, the specific on resistance (Ron,sp) and breakdown voltage (BV) of the proposed SJ LDMOS are reduced by 60.09% and 28.9% compared with those of the conventional SJ LDMOS, respectively. With the increase of the drift region length, the SJ LDMOS which eliminates the SAD effect has more obvious advantages in the high voltage field.

Detailed total ionizing dose effects on LDMOS transistors

The degradation of lateral double-diffused MOSFETs (LDMOS) due to total ionizing dose (TID) effects is examined in this paper using physics-based 2D TCAD simulations. The devices under test (DUTs) are built with a single reduced surface field (single-RESURF) structure and local oxidation of silicon (LOCOS) field oxide. The device structure was chosen for its topological simplicity in comparison to other modern LDMOS transistors to explore the impact of gamma radiation on small-AC and RF behavior. The results demonstrate fundamental differences between n-type (nLDMOS) and the p-type (pLDMOS) parameter shifts. Due to the distinct damage location in the pLDMOS, which is mainly the drift region, TID augments the values of the various parasitic capacitances. However, in the nLDMOS, TID reduced those values, especially the gate capacitance overshoot, as the degradation happens in the channel region and the bird's beak mostly. Consequently, the RF response and stability of the devices will differ. In addition, we present new research opportunities for TID effects on LDMOS transistors in particular, but also for radiation studies in general.

A TCAD Study on High-Voltage Superjunction LDMOS with Variable-K Dielectric Trench

In this paper, a novel high voltage superjunction lateral double diffused MOSFETs (SJ-LDMOS) using a variable high permittivity (VHK) dielectric trench is presented. A relatively high HK dielectric is in the upper trench, which is connected with the drain electrode to suppress the high electric field (E-field) peak under the drain by the dielectric reduced surface field (RESURF) effect. In addition, a relatively low HK dielectric is at the bottom of the trench. On the one hand, the substrate is effectively depleted by a suitable HK dielectric layer, and the vertical depletion region of the substrate is greatly expanded. On the other hand, the overall vertical bulk E-field distribution is modulated by the E-field peaks generated at the position of varying K dielectric. A more uniform bulk E-field distribution is obtained for VHK SJ-LDMOS, leading to a high breakdown voltage (BV). Compared to the conventional SJ-LDMOS, the blocking voltage per micron of the drift region of VHK SJ-LDMOS has increased by 41.2%. Besides, compared with the SJ-LDMOS with a uniform-K, the BV of VHK SJ-LDMOS is improved by about 9.5%. The condition of the optimal range of the variable high permittivity is also presented. Meanwhile, the proposed VHK SJ-LDMOS has good conduction characteristics and heat dissipation

New Strained Lateral MOSFET With Ultralow On-Resistance by Surrounded Stress Dielectric Layer

A novel ultralow on- resistance strained lateral double-diffused MOSFET with surrounded stress dielectric layer (SSDL LDMOS) is proposed in this letter. The surrounded stress dielectric layer (SSDL) as a stressor introduces an enlarged beneficial stress in the drift region by superimposing the stresses from three directions to enhance the electron mobility. Besides, SSDL combines with the extended gate electrode to assist in depleting the N-drift region in the off state and accumulate electrons on the surface of N-drift region in the on state, which leads to an allowable highly-doped N-drift region and a low-resistance current path, respectively. As a consequence, SSDL LDMOS realizes an ultralow specific on- resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula>) resulting from the improved electron mobility, highly-doped N-drift region and low-resistance current path. The simulation results show that SSDL LDMOS exhibits a 37&#x0025; reduction in <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> relative to the folded accumulation LDMOS (FALDMOS). The figure-of-merit (<i>FOM</i>) of SSDL LDMOS increases from 17.1 MW/cm² of Cov. LDMOS and 33.5 MW/cm² of FALDMOS to 42.0 MW/cm², which realizes a superior performance.

Cut-Off Degradation of Output Current Induced by High Fluence Neutron Radiation in High-Voltage Silicon-on-Insulator Lateral Double-Diffused MOSFET

In this letter, a novel cut-off degradation of output current induced by high fluence neutron radiation is investigated for high-voltage silicon-on-insulator lateral double-diffused MOSFET (HV SOI LDMOS). Unlike low/middle fluence, severe current collapse occurs at low drain voltage. Combining experiments and energy band analysis, we reveal that a secondary charge removal effect leads to cut-off degradation, which is closely related to the field enhancement and high-density defects at high neutron fluence. Although the gate channel can be turned on after radiation, below drain threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {DT}}$ </tex-math></inline-formula> ), electron drift is blocked by a potential barrier caused by the local space charge region with low trap occupation rate, rather than the global impact at low fluence. In addition, the influences of structural parameters on the cut-off degradation and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {DT}}$ </tex-math></inline-formula> are studied to guide the rad-hardening design of HV SOI LDMOS.

Simulation Study of A 1200V 4H-SiC Lateral MOSFET With Reduced Saturation Current

A 1200V 4H-SiC lateral double-diffused MOSFET (LDMOS) featuring a lightly doped P-top layer at the source side, and a high-doped N-well layer arranged between the channel and P-top layer is proposed. In order to promote the simulation accuracy, Sentaurus Process Tool that can simulate the oxidation, ion implantation, annealing, diffusion, etc. is used for structure establishment in this letter. In the ON-state, the electric potential at the end of the channel can be modulated and lowered due to the existence of P-top layer. The P-top layer can shield the voltage from the drain side, which results in the reduced saturation current ( $\text{I}_{\text {dsat}}$ ), especially at high drain-source voltage ( $\text{V}_{\text {DS}}$ ). The introduction of the N-well layer ensures that the P-top layer has almost no impact on the linear current ( $\text{I}_{\text {dlin}}$ ). Compared with the conventional SiC LDMOS, the $\text{I}_{\text {dsat}}$ at $\text{V}_{\text {DS}}\,\,=400\text{V}$ of the proposed LDMOS decreases by 24.2% with no degradation in the $\text{I}_{\text {dlin}}$ and the OFF-state breakdown voltage (BV). Benefiting from the suppressed $\text{I}_{\text {dsat}}$ , the proposed SiC LDMOS achieves a ON-state BV 366V higher than that of the conventional SiC LDMOS at the gate-source voltage of 20V. Since the short-circuit capability of the SiC power devices is much sensitive to the $\text{I}_{\text {dsat}}$ , the 24.2% reduction in $\text{I}_{\text {dsat}}$ can predict a considerable enhanced short-circuit capability. Simulation results show that the short-circuit withstand time can be improved by 105%.

Analytical Study on a 700 V Triple RESURF LDMOS With a Variable High-K Dielectric Trench

A novel 700 V triple REduced SURface Field (RESURF) lateral double-diffused MOSFETs (LDMOS) with a variable high- K (VHK) dielectric trench for smart power applications is proposed and studied by TCAD simulations. Compared with conventional triple RESURF (CTR) LDMOS, the new structure features a composite high- K (HK) dielectric trench embedded in the drain edge. First, a higher HK dielectric layer is in the upper trench to suppress the high electric field ( E-field) under the drain by dielectric RESURF. Second, a lower HK dielectric is at the bottom of the trench to promote the depletion of the N-buffer layer and P-substrate, which increases the N-buffer doping concentration and thus reduces ON-resistance. The overall vertical bulk E-field distribution is modulated by the E-field peak generated at the position of varying K dielectric, which greatly improves breakdown voltage (BV). An analytical model of BV and vertical E-field taking account of the influence of the VHK dielectric trench is presented. Simulation results show that the proposed VHK TR LDMOS is able to obtain a 30.2% higher BV and a lower 15.4% R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON, sp</sub> than the CTR LDMOS. Moreover, the figure of merit (BV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> ) of VHK TR LDMOS has doubled further breaking the lateral silicon limit.

Accumulation-Mode Lateral Double-Diffused MOSFET Breaking Silicon Limit by Eliminating Dependence of Specific ON-Resistance on Doping Concentration

An accumulation-mode lateral double-diffused MOSFET (LDMOS) is proposed and its mechanism is investigated in this article. To optimize the tradeoff between breakdown voltage (BV) and specific ON-resistance ( ${R}_{\text {on,sp}}$ ), the idea of separating the breakdown area from the conduction path is designed. The N-type buffer layer is adopted to obtain ideal reverse characteristics for accumulation-mode LDMOS. The electrons are introduced to eliminate the dependence of the ${R}_{\text {on,sp}}$ on the doping concentration of the drift region. Simulation results show that the ${R}_{\text {on,sp}}$ of the proposed LDMOS is 6.83 $\text{m}\Omega \cdot \text {cm}^{{2}}$ with the BV of 460 V, which is less than 30.2 $\text{m}\Omega \cdot \text {cm}^{{2}}$ that of the conventional LDMOS with the BV of 223 V for the same drift region length of $20~\mu \text{m}$ . Moreover, the ${R}_{\text {on,sp}}$ of ac-NBL LDMOS is only 2.07 $\text{m}\Omega \cdot \text {cm}^{{2}}$ , which is reduced by 93% compared with the conventional LDMOS with the same BV of 223 V. A better tradeoff between BV and ${R}_{\text {on,sp}}$ can be obtained by eliminating the dependence of ${R}_{\text {on,sp}}$ on the doping concentration, and the ${R}_{\text {on},\text {sp}}$ of ac-NBL LDMOS increases much more slowly than that of conventional LDMOS as BV increases.

Improved Model on Buried-Oxide Damage Induced by Total-Ionizing-Dose Effect for HV SOI LDMOS

In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.

Performance Boosts in n-Type Lateral Double-Diffused MOSFET With Process-Induced Strain Using Contact Etch Stop Layer Stressor

In this brief, the contact etch stop layer (CESL) stressor is introduced to improve the performance of n-type lateral double-diffused MOSFET (nLDMOSFET) with various operating voltages. Three groups of nLDMOSFETs were studied to demonstrate the effects of the CESL stressor. The electrical properties were carefully characterized, and the tip-enhanced Raman spectroscopy measurements were carried out to examine the process-induced strain directly. It is found that nLDMOSFETs with the strained SiN CESL have larger output current, transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ), and higher breakdown voltage (BV). The strained SiN CESL introduces tensile strain in the device and results in the performance boosts, which are verified by negative Raman peak shift mappings and TCAD simulations. The strained SiN CESL could effectively decrease the specific ON-resistance (Ron) and improve the BV of the nLDMOSFET, due to the mobility enhancement.

Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers

Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.

A Novel Ultralow R ON,sp Triple RESURF LDMOS With Sandwich n-p-n Layer

This article proposes a novel ultralow specific ON-resistance (RON,sp) triple reduced surface field (RESURF) lateral double-diffused MOSFET (LDMOS) with sandwich np-n layer. Compared with the conventional triple RESURF LDMOS with n-type top layer (NTTR LDMOS), the new structure is characterized by an additional N-buried layer below the P-buried layer. Due to the introduction of N-buried layer, the concentration of N-top layer will decrease to ensure charge balance, thus making the surface electric field distribution better and the higher additional doping introduced by N-top and N-buried layers can be achieved. The dose and implantation energy of n-p-n layers were simulated and optimized. Furthermore, in order to eliminate the premature avalanche breakdown occurring in the source-centered termination region, substrate termination technology (STT) is applied to avoid the high electric field peaks generated in the curved source region with small curvature radius. But the use of STT makes it easy to breakdown in the transitional region compared with the straight region. Therefore, the transitional region is studied and the crucial parameter AL in the layout of transitional region is also optimized. The fabricated device experimentally demonstrated improved performance with low R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> of 78.3 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and high breakdown voltage (BV) of 795 V, and the experimental R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON,sp</sub> is 26.8% lower than that of the conventional triple RESURF LDMOS (CTR LDMOS) and 10% lower than that of the NTTR LDMOS based on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> = 67 μm, which can break the silicon limit of CTR and NTTR LDMOS and meet the demand of 700-V high-voltage integrated circuit applications.