Simulation Study of A 1200V 4H-SiC Lateral MOSFET With Reduced Saturation Current

Abstract

A 1200V 4H-SiC lateral double-diffused MOSFET (LDMOS) featuring a lightly doped P-top layer at the source side, and a high-doped N-well layer arranged between the channel and P-top layer is proposed. In order to promote the simulation accuracy, Sentaurus Process Tool that can simulate the oxidation, ion implantation, annealing, diffusion, etc. is used for structure establishment in this letter. In the ON-state, the electric potential at the end of the channel can be modulated and lowered due to the existence of P-top layer. The P-top layer can shield the voltage from the drain side, which results in the reduced saturation current ( $\text{I}_{\text {dsat}}$ ), especially at high drain-source voltage ( $\text{V}_{\text {DS}}$ ). The introduction of the N-well layer ensures that the P-top layer has almost no impact on the linear current ( $\text{I}_{\text {dlin}}$ ). Compared with the conventional SiC LDMOS, the $\text{I}_{\text {dsat}}$ at $\text{V}_{\text {DS}}\,\,=400\text{V}$ of the proposed LDMOS decreases by 24.2% with no degradation in the $\text{I}_{\text {dlin}}$ and the OFF-state breakdown voltage (BV). Benefiting from the suppressed $\text{I}_{\text {dsat}}$ , the proposed SiC LDMOS achieves a ON-state BV 366V higher than that of the conventional SiC LDMOS at the gate-source voltage of 20V. Since the short-circuit capability of the SiC power devices is much sensitive to the $\text{I}_{\text {dsat}}$ , the 24.2% reduction in $\text{I}_{\text {dsat}}$ can predict a considerable enhanced short-circuit capability. Simulation results show that the short-circuit withstand time can be improved by 105%.