New Strained Lateral MOSFET With Ultralow On-Resistance by Surrounded Stress Dielectric Layer

Abstract

A novel ultralow on- resistance strained lateral double-diffused MOSFET with surrounded stress dielectric layer (SSDL LDMOS) is proposed in this letter. The surrounded stress dielectric layer (SSDL) as a stressor introduces an enlarged beneficial stress in the drift region by superimposing the stresses from three directions to enhance the electron mobility. Besides, SSDL combines with the extended gate electrode to assist in depleting the N-drift region in the off state and accumulate electrons on the surface of N-drift region in the on state, which leads to an allowable highly-doped N-drift region and a low-resistance current path, respectively. As a consequence, SSDL LDMOS realizes an ultralow specific on- resistance (<inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula>) resulting from the improved electron mobility, highly-doped N-drift region and low-resistance current path. The simulation results show that SSDL LDMOS exhibits a 37&#x0025; reduction in <inline-formula> <tex-math notation="LaTeX">${R}_{\text {on,sp}}$ </tex-math></inline-formula> relative to the folded accumulation LDMOS (FALDMOS). The figure-of-merit (<i>FOM</i>) of SSDL LDMOS increases from 17.1 MW/cm² of Cov. LDMOS and 33.5 MW/cm² of FALDMOS to 42.0 MW/cm², which realizes a superior performance.