Abstract
In this article, an improved model on buried-oxide (BOX) damage induced by total-ionizing-dose (TID) effect considering positive oxide trapped charge ( N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> ) generated in silicon on insulator (SOI)/BOX interface under negative electric field bias (field lines perpendicular to the SOI/BOX interface pointing from the top to the bottom of the BOX) and N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ot</sub> saturation effect is proposed and adopted in accurate simulated analysis to predict the postirradiation device behavior. Moreover, the mechanism of high-voltage (HV) SOI lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) degradation during irradiation is also revealed by the proposed accurate simulation method. Tolerance design for radiation-hardened HV SOI LDMOS is discussed with the aid of the presented model. The tradeoff between postirradiation electrical characteristics and fresh electrical characteristics should be taken into account to meet the radiation hardening requirement. The radiation-hardened-by-design LDMOS introduced in this article keeps an OFF-state breakdown voltage above 120 V at D = 500 krad(Si) with operating voltage equal to 80 V, which is fabricated on a commercial SOI substrate material with plain interface quality parameters. The corresponding hardening strategy is also given.
Highlights
A S SPACE power electronics system grows toward smaller size and weight, higher integration level and performance are required
Electron–hole pairs are created in oxide layer by γ -ray radiation, where the holes are attracted toward the silicon on insulator (SOI)/BOX interface, part of them are trapped by trapping centers located in the region close to the SOI/BOX interface
The implantation doses of N-drift region (DN) are 0.6 × 1012 and 1.4 × 1012 cm−2 for the radiation-hardened HV SOI LDMOS and the conventional RESURF HV SOI LDMOS, respectively
Summary
A S SPACE power electronics system grows toward smaller size and weight, higher integration level and performance are required. It is hard to predict the Not distribution in BOX under OFF-state bias in the postirradiation device and the traditional model for TID effect is not applicable for HV SOI LDMOS at OFF-state in the simulated analysis. The distribution of radiation-induced Not in BOX with different applied electric fields for HV SOI LDMOS is investigated. In contrast to the traditional model which depends upon Not buildup near the interface that the field lines point to, the verified experimental results in this article indicate that there is still a nonnegligible set of Not generated in SOI/BOX interface even if the electric field plays a negative role, which is responsible for the electrical characteristic shift behavior. With operating voltage equal to 80 V, which is fabricated on a low-cost and highly accessible commercial SOI substrate material without radiation-hardening-by-process
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