TID Effect of MOSFETs in SOI BCD Process and Its Hardening Technique

Abstract

The TID effect of low operation voltage MOSFET (LV-MOS), medium operation voltage lateral double-diffused MOSFET (MV-LDMOS), and 600V high operation voltage LDMOS (HV-LDMOS) manufactured by SOI BCD process is investigated by experiments and 3D TCAD numerical simulations and the hardening technique is proposed and discussed. The experiment and simulation results of LV-MOS with three different structures indicate that the TID-induced leakage current is mainly caused by the STI oxide, which forms a leakage current path along the side of channel region. The leakage current of LV-MOS with a square/ring shape gate structure does not increase even though the irradiation dose increases to 300 krad(Si). The square/ring shape gate structure can eliminate the TID-induced leakage current induced by segregating the channel from STI region, which is used in MV-LDMOS and 600V HV-LDMOS. The TID-induced leakage current of radiation-hardened MV-LDMOS does not increase at the irradiation dose of 300 krad(Si). The TID-induced leakage current of radiation-hardened 600V HV-LDMOS is about four orders of magnitude less than that of standard 600V HV-LDMOS at the irradiation dose of 50 krad(Si). The specific-on-resistance performance of MV-LDMOS and 600V HV-LDMOS is improved with the increase of irradiation dose. The radiation-hardened technique used in this paper can improve the TID tolerance of MOSFETs in SOI BCD process significantly. The systematic and thorough investigation of TID hardening technique of SOI BCD technology will contribute to the application of power ICs in space environment.