Reducing the specific on-resistance for a trench-gate-integrated SOI LDMOS by using the double silicon drift layers

Abstract

Double silicon drift layers are used to reduce the specific on-resistance (Ron,sp) for a trench-gate-integrated lateral double-diffused MOSFET (DDL TG LDMOS) based on SOI technology in this paper. A trench-gate is incorporated into the oxide trench, a n-type drift layer with a high doping concentration is introduced on the topside of the original drift layer around the oxide trench, and a p-type pillar layer with a high doping concentration is inserted between the dual drift layers. First, the incorporated trench-gate constitutes dual current conduction channels, which decreases the Ron,sp. Second, the whole electric fields on the device surface and around the oxide trench are modulated on the basis of RESURF condition, leading to a higher breakdown voltage (BV) at off-state. Finally, the doping concentration of the drift layers is increased by an assistant depletion effect from the p-pillar, which not only improves the BV but also reduces the Ron,sp. Consequently, compared with those of the conventional trench SOI LDMOS on the same drift region of 18 μm and top silicon layer of 25 μm, a higher BV of 477 V and a lower Ron,sp of 32.1 mΩ∙cm2 are obtained for the DDL TG SOI LDMOS, while BV is improved by 33.5% and Ron,sp is reduced by 92.9%, respectively.