Junctionless Field Effect Transistor Research Articles

Performance Analysis of Multi-Channel-Multi-Gate-Based Junctionless Field Effect Transistor

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower I off current of 4.34 × 10−19 A, an I on current of 4.17 × 10−06 A with an I on/I off current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices.

Comprehensive study of gate induced drain leakage in nanowire and nanotube junctionless FETs using Si1-xGex source/drain

We present, in this paper, optimized nanotube (NT) and nanowire (NW) junctionless field-effect transistor (JLFET) architectures of gate-induced drain leakage (GIDL). At the source/ drain–channel interface, SiGe creates a valence energy band discontinuity which alleviates lateral band-to-band tunneling (L-BTBT) of electrons in the OFF-state. It is established through 2-D TCAD simulations that inclusion of SiGe decreases L-BTBT in the NTJLFET by >5 orders, thus leading to a substantial ION/IOFF of with precision 1012 for a 20 nm gate length which is not attainable in the conventional NTJLFET (ION/IOFF ∼ 106). Furthermore, degraded OFF-state current in NWJLFET because of conventional charge-sharing effect improves with the inclusion of SiGe by ∼2 orders of magnitude. Additionally, it is effective to place SiGe layers positioned at the source and drain regions and SiGe/ Si interface inside or at the channel region. Based on the proposed design guidelines, we show that the optimized SiGe S/D NTJLFET is effective in reduction of L-BTBT GIDL when gate length is scaled to 5 nm.

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.

Performance analysis of short channel effects immune JLFET with enhanced drive current

AbstractThis manuscript reports analog/RF and noise analysis of a novel junctionless field effect transistor. To reduce the gate induced drain leakage (GIDL), step‐gate‐oxide structure is used with a high‐k buried oxide (BOX) which subsequently reduces IOFF. The off current and gate capacitance is reduced by including step‐gate‐oxide in high k‐BOX JLFET due to increase in the band to band tunneling (BTBT) width. The DIBL is reduced significantly to 0.014 which is 60% less as compared to high‐k BOX JLFET (HB JLFET). For different length and thickness of the step‐gate‐oxide, the analog/RF and noise performance of the step‐gate‐oxide JLFET with high‐k BOX (SGO HB JLFET) have also been investigated in detail. Silvaco TCAD simulation of the proposed structure for 20 nm channel length shows an extremely high ION/IOFF ratio of ~108. The subthreshold swing for the simulated structure was also found to be considerably low (82 mV/dec).

BTBT Based LIF Junctionless FET Neuron With Plausible Mimicking Efficiency

Amid the quest for nanoscale devices to mimic the biological neuronal dynamics, this article demonstrates a SOI Junctionless Field Effect Transistor (JLFET) based leaky integrate and fire (LIF) neuron in sub-20 nm technology. The band-to-band-tunneling (BTBT) mechanism is considered to imitate the leaky-integration behavior. As JLFET has strongly doped channel that supports fully depletion in the OFF state with considerable band overlapping of channel and drain regions that is subsequently allowing the BTBT in lateral direction. Moreover, the proposed device based LIF neuron requires neither metallurgical junction nor back gate bias to induce the floating body to confine the excess carrier. And, it requires only 0.4 V of supply voltage, which is much lower compared to its equivalent bulk FinFET and PD-SOI MOSFET based LIF neurons and it shows a GHz range of spiking frequency i.e., <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 8 orders greater than biological neuron. Hence, it presumes that the proposed SOI JLFET based LIF neuron is more suitable for large scale hardware implementation of spiking neural network (SNN) due to its energy and area efficiency comparable with biological neuron along with CMOS compatibility.

Thermoemission-Based Model of THz Detection and Its Validation—JLFET Case Studies

Silicon junctionless field-effect transistors (JLFETs) detect THz radiation even at frequencies above a few THz. This effect cannot be explained by classic laws of electron transport. The same behavior is observed for other types of FETs. However, the JLFET architecture makes this device an effective tool for testing the THz detection mechanism. In particular, a deeper insight into this effect is provided by a case study in which, the low concentration of electrons in the gate-controlled region contradicts potential plasmonic effects. Considering the experimental results, the authors critically discuss the plasmon-based theory of THz detection by JLFETs. Then, taking into account the revealed inconsistencies and based on numerical simulation results, they propose a simple, one-dimensional JLFET photoresponse model based on local electron heating at the channel–source contact which is located in the path of the THz signal between the gate and the source. The model is verified in a simulation-assisted experiment showing that the energy of hot electrons generates a sufficient photoelectric voltage, typical of silicon FETs integrated with antennas illuminated by THz radiation. The authors suggest that the model is universal and in the three-dimensional version it can successfully explain the THz detection by various FETs, especially those operating in the subthreshold range in which the electron concentration under the gate is very low.

Radiation study of TFET and JLFET-based devices and circuits: a comprehensive review on the device structure and sensitivity

All electronic devices when used in a radiation environment undergo significant changes in their electrical properties. It is interesting to explore the effects of radiation, not only on conventional MOSFET devices but also on novel devices like FinFET, Tunneling Field Effect Transistor (TFET), and Junctionless Field Effect Transistor (JLFET). This study presents a systematic review of radiation studies on TFET and JLFET-based devices/circuits. TFET and JLFET have gained popularity in recent days due to their wide use in ultra-scaled designs than conventional CMOS. The effect of radiation on a divergent range of TFET and JLFET devices and circuits is explored. The variations in DC characteristics and electrical parameters under the influence of radiation strikes are analyzed in detail. The radiation effects like Total Ionizing Dose (TID), and Single Event Upset (SEU) are noted for these devices/circuits. The radiation study on different devices shows that these devices are sensitive to Single Event Effect (SEE), steeper Subthreshold Swing (SS), increase in Electron Hole Pair (EHP) production, increase in drain current (ID), and increase in collected charge (QC), decrease in bipolar gain and trans-conductance.

Vertical gate cavity bulk-planar junctionless FET-based biosensor for label-free detection of biomolecules

In this paper, we propose a vertical gate bulk-planar junctionless field-effect transistor (VGC-BPJLFET)-based biosensor for the label-free detection of neutral and charged target biomolecules. The vertical gate structure exhibits better performance due to high gate controlability in the channel region, which improves the drain current of the device. The enhancement in drain current significantly increases the sensing capability of the biosensor. To sense the neutral (APTES, biotin, streptavidin, protein, etc) and charged (deoxyribonucleic acid (DNA)) target biomolecules, the VGC-BPJLFET biosensor includes a vertical nanogap cavity in between the gate electrodes of the device in which HfO2 behaves as the functionalization layer. However, for the detection of both neutral and charged biomolecules, the two electric parameters (dielectric constant (K) and the charge density (ρ)) are considered in the etched nanogap cavity. Furthermore, to see the potentiality of the VGC-BPJLFET biosensor, the proposed biosensor has been compared to the lateral gate cavity BPJLFET biosensor in terms of drain current, sensitivity, linearity and signal-to-noise ratio characteristics. From the comparison, it has been observed that the proposed device has a higher sensitivity of ∼104 and ∼103 with the conjugation of neutral (APTES (K = 3.57)) and charged (DNA (ρ = −1 × 1011 cm−2)) biomolecules, respectively. The VGC-BPJLFET biosensor also carries the better sensing capability to sense the target biomolecules with the presence of unwanted (air) biomolecules in the etched nanogap cavity.

Realization of Double‐Gate Junctionless Field Effect Transistor Depletion Region for 6 nm Regime with an Efficient Layer

Herein, the authors suggest a junctionless field effect transistor with an embedded p‐type layer (EPL‐JLT) near the drain channel side, employing calibrated structure simulations to obtain a complete depletion region in a 6 nm channel length. The incorporation of a p‐type layer improves leakage current (I OFF) and subthreshold swing (SS) for a 6 nm regime structure at 5.9 eV work function (WF) while the ON current (I ON) diminishes a little. This considerable achievement in the leakage current enables obtaining multiple threshold voltages (V TH) by adjusting the gate WF. The goal aids in creating optimized structures, which is impossible in silicon JLFETs (Si‐JLT) due to their requirement for large WFs to obtain a depletion region even at higher channel lengths. The proposed device has a leakage current of 1 nA μm−1 even at a 5.1 eV WF. The scaling of the EPL‐JLT for different channel lengths is investigated.

Planar Junctionless Field-Effect Transistor for Detecting Biomolecular Interactions.

Label-free field-effect transistor-based immunosensors are promising candidates for proteomics and peptidomics-based diagnostics and therapeutics due to their high multiplexing capability, fast response time, and ability to increase the sensor sensitivity due to the short length of peptides. In this work, planar junctionless field-effect transistor sensors (FETs) were fabricated and characterized for pH sensing. The device with SiO2 gate oxide has shown voltage sensitivity of 41.8 ± 1.4, 39.9 ± 1.4, 39.0 ± 1.1, and 37.6 ± 1.0 mV/pH for constant drain currents of 5, 10, 20, and 50 nA, respectively, with a drain to source voltage of 0.05 V. The drift analysis shows a stability over time of −18 nA/h (pH 7.75), −3.5 nA/h (pH 6.84), −0.5 nA/h (pH 4.91), 0.5 nA/h (pH 3.43), corresponding to a pH drift of −0.45, −0.09, −0.01, and 0.01 per h. Theoretical modeling and simulation resulted in a mean value of the surface states of 3.8 × 1015/cm2 with a standard deviation of 3.6 × 1015/cm2. We have experimentally verified the number of surface sites due to APTES, peptide, and protein immobilization, which is in line with the theoretical calculations for FETs to be used for detecting peptide-protein interactions for future applications.

Improved DC Performance of Nanotube Junctionless Field-Effect Transistors with Dielectric Pocket Integration

In this paper, a nanotube architecture of Junctionless FET (JLFET) is investigated wherein it is observed that the performance characteristics of JLFET are improved by introducing Dielectric Pockets into the device near the source-channel and channel-drain interfaces by coming up with a novel structure of nanotube junctionless FET (NTJLFET) called as Dielectric Pocket-NTJLFET (DP-NTJLFET). Using TCAD tool, the proposed DP-NTJLFET has been simulated for a channel length of 20 nm in order to consider and show the improvement in various short-channel effects. The inclusion of Dielectric Pockets into the device significantly reduced the OFF-state current, which eventually improved the current switching ratio (∼2600%) for a pocket length and thickness of 4 and 7 nm, respectively. Further, the proposed device exhibits an improved subthreshold swing characteristics and a better measure of DIBL (improved by ∼12%) for DP-NTJLFET as compared to the conventional NTJLFET. As a result of achieving low OFF-state current, the proposed DP-NTJLFET may be found suitable for the future low-power applications.

A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement

In this paper, we report, the hot carrier reliability issue in the Si1-xGex source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of ΔEg = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1-xGex S/D architecture shows better immunity than the conventional NTJLFET. The Si1-xGex S/D enhances the reliability of analog/RF parameters such as transconductance (gm), intrinsic gain (gm/gd), cut-off frequency (fT), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced gm, and lower fT. The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1–xGex S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters.

A Charge-Based Analytical Model for Gate All Around Junction-Less Field Effect Transistor Including Interface Traps

This article proposes an analytic charge-based model that incorporates interface trapping. The model’s applicability to all operating zones includes various interface trap charges with varying doping concentrations. Using the analytical model, the impact of interface traps on different electrical parameters, such as channel potential, surface potential, electric field, and drain current, is examined. The transconductance and cut-off frequency models are also developed from the drain current model. To validate our model, the analytical model results were compared with the TCAD device simulation results and available experimental data from literature. The Fermi level location of interface traps greatly influences surface potential in the bandgap, leading to subthreshold deterioration and flat band shifting in Junction Less Field Effect Transistor (GAAJLFET) with SiO2 as a gate insulator, which leads to performance degradation of different device parameters. To decrease the impact of the interface trap on the device’s characteristics without impairing the performance, a suitable device with SiO2 and high-k gate-stack as an insulator is designed and compared with GAAJLFET with SiO2 as a gate insulator. A GAAJLFET with SiO2 as an insulating material has very different device parameters than a GAAJLFET with SiO2 and high-k gate-stack as a gate insulating material.

Digital Circuit Performance Evaluation of Parallel Gated Junctionless Field Effect Transistor

This paper reports the modeling and performance enhancement of complementary metal-oxide-semiconductor (CMOS) inverters using parallel-gated junctionless field-effect transistors (PGJLFET). A mathematical model for different parameters, namely, low and high input voltage, low and high output voltage, noise margin, rise time, fall time, propagation delay, and power dissipation of the inverter circuit was established. To establish the model for various parameters, potential models at the source-channel boundary and the potential at the drain-channel boundary are considered. The variations in the voltage transfer characteristics of the output current with respect to the input voltage and the power dissipation with respect to the input voltage for steady-state conditions and transient states were investigated for different gate dielectrics, gap lengths, and gate oxide thicknesses. The models were validated by comparing them with technology computer-aided design (TCAD) simulation results. The noise margin, rise time, fall time, and propagation delay of the PGJLFET-based inverter are estimated and compared with those of a conventional junctionless transistor. It has been observed that the PGJLFET exhibits an improvement in the noise margin and propagation delay compared with conventional junctionless transistors.

Effect of geometry and temperature variations on sensitivity and linearity of junctionless pH sensing FET: An experimental study

Here-in this work, boron doped poly-silicon based dimensional variants of thin film planar junctionless field effect transistors are fabricated through CMOS compatible process for pH detection. The dimensional variants are classified into two sets as set-1 (channel length, L = 100 μm) and set-2 (channel length, L = 120 μm) with widths of 3 μm, 5 μm, 10 μm, and 20 μm. Sensitivity of the fabricated devices is analyzed using phosphate buffer saline solutions of pH 3.1, 5.2, 7, 9 and 11.2 and is computed in terms of relative shift in threshold voltage (VTh) and maximum drain current (IDS). The reference VTh and IDS are taken at neutral pH 7. Here we have experimentally analyzed the effect on pH sensitivity by varying the device widths and temperatures from 30 °C to 50 °C. It is observed that varying the device width from 3 μm to 20 μm, VTh sensitivity reduces from 19.08% to 9.17% and from 16.03% to 8.5% for set-1 and set-2 devices respectively. Increasing temperature from 30 °C to 50 °C causes reduction of VTh sensitivity from 18.68% to 13.52% for device with W/L = 3μm/100 μm and 16.78%–10.99% for device with W/L = 3μm/120 μm. The reduction in width causes average VTh sensitivity to roll-off by 0.49%/μm and 0.26%/μm for L = 100 μm and L = 120 μm respectively. Also the increase in operating temperature from 30 °C to 50 °C leads VTh sensitivity to roll-off by 0.17%/°C and 0.2%/°C for W/L = 3μm/100 μm and W/L = 3μm/120 μm respectively.

Carrier Mobility Analysis of Parallel Gated Junctionless Field Effect Transistor

The paper reports analysis of carrier mobility in a Parallel Gated Junctionless Field Effect Transistor. Fully analytical mathematical models for electron and hole mobilities are developed. The mobility models are developed using empirical relation between mobility and transverse and longitudinal electric field. The Quantum confinement effect has also been considered in the models. In the model electric field dependence on classical and quantum mechanical effects are formulated separately. The total electric field is the summation of the two. The models are compared with Technology Computer-Aided Design simulation results. The simulation results show that the parallel gated structure exhibits higher electron as well as hole mobility compared to that of a conventional Junctionless Field Effect Transistor. It can also be seen that the carrier mobility enhances with longer gap length due to reduced longitudinal electric field. As the models are analytical in nature and agree reasonably with numerical simulation results obtained from TCAD the models are suitable for compact modeling.

Split-Gate Induced High-Field for Impact Ionization Triggered Bipolar Action and Sub-kT/q Switching in Junctionless FET

In this article, an energy-efficient, ultra-steep subthreshold slope device based on the split-gate junctionless field-effect transistor (JLFET) has been proposed and investigated. Through split-gate, two regions, namely, channel-1 and channel-2, separated by a gap (<inline-formula><tex-math notation="LaTeX">$L_{gap}$</tex-math></inline-formula>) are created. A high electric field is thus induced at the interface of these two regions, which initiates impact ionization (II) at sub-bandgap drain voltage. The II-generated holes/electrons accumulate in channel-2 of N-JLFET/P-JLFET and set up a floating body that reduces the potential barrier between channel-1 and source of the device resulting in ultra-steep switching. Using a well-calibrated TCAD tool, we analyzed the operation of both N- and P-JLFET. A subthreshold swing (SS) of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> 50&#x00A0;<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>V/decade over nearly three decades of drain current is possible while maintaining a low OFF current of <inline-formula><tex-math notation="LaTeX">$\sim$</tex-math></inline-formula> <inline-formula><tex-math notation="LaTeX">$4.9\times 10^{-12}$</tex-math></inline-formula> A/<inline-formula><tex-math notation="LaTeX">$\mu$</tex-math></inline-formula>m at a drain voltage of 0.4&#x00A0;V for silicon N-JLFET, which is better than any of the results reported so far for the junctionless devices. We have also investigated the impact of various device design parameters such as lengths of channel-1, channel-2, channel doping concentration, <inline-formula><tex-math notation="LaTeX">$L_{gap}$</tex-math></inline-formula>, gate oxide thickness and its permittivity, channel thickness, and dual-metal work function on the device performance.

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

An Analytical Model for the Depletion Region Width and Threshold Voltage of a Parallel Gated Junctionless Field Effect Transistor

Effect of Work-function Variation on Transfer Characteristics and Memory Performances for Gate-all-around JLFET based Capacitorless DRAM

In this study, we present variations in transfer characteristics and memory performances caused by work-function variation (WFV) in the metal gate of a one-transistor dynamic random-access memory cell based on a gate-all-around junctionless field-effect transistor (GAA-JLFET). To investigate the influence of WFV, we simulated 200 samples of GAA-JLFETs. The samples had different transfer characteristics depending on the metal grain granularity. In addition, we calculated and analyzed the mean and standard deviations for the transfer characteristics. Further, the memory performances were analyzed using two extreme cases with the highest and lowest threshold voltage (V<SUB>th</SUB>) as examples. When WFV was not considered, the current ratio was 108, and retention time was more than 10 ms. Meanwhile, when WFV was considered, the current ratio was 10² and 10⁴, and the retention time was reduced to 0.051 ms and 2.2 ms, respectively. These results showed that WFV affected not only the transfer characteristics in GAA-JLFET but also the memory performances; it could adversely affect the reliability of the memory device.

Leakage mitigation in NW FET using negative Schottky junction drain and its process variation analysis

In this work, a Schottky junction on the drain side employing low workfunction (WF) metal is proposed as a method to suppress the OFF-state leakage in nanowire (NW) field-effect transistor (FET). Instead of a highly n+ doped drain, low WF metal with negative electron Schottky barrier height (SBH) as a drain minimizes the lateral band-to-band tunneling (L-BTBT) considerably. L-BTBT is the movement of carriers (holes) from the drain conduction band into the channel valence band during the OFF-state. Impact of varying WF at channel–drain junction on the device characteristics is studied. It is observed that SBH \(\leqslant 0\) eV is required to mitigate L-BTBT compared to the conventionally doped and junctionless (JL) NW counterpart. Furthermore, unlike L-BTBT, leakage in NW Schottky drain (SD) comprises of holes tunneling through the SB from the metal drain into the channel and is termed as the lateral SB tunneling (L-SBT). In contrast with JL NW FET, the process variation immunity (varying channel doping, \({N}_{\mathrm{Ch}}\) and NW diameter, \({d}_{\mathrm{NW}}\)) and the ON-state current of the proposed device are not compromised at the expense of lower OFF-state L-SBT. Instead, the device is less susceptible to process variations and retains the ON-state performance of the NW MOSFET. For a ± 20% change in \({N}_{\mathrm{Ch}}\), \(\Delta {I}_{\mathrm{OFF}}\)/\({I}_{\mathrm{OFF}}\) of 7% compared to 97% in NW JL FET is observed.