Performance Analysis of Multi-Channel-Multi-Gate-Based Junctionless Field Effect Transistor

Abstract

In this paper, a multi-gate junctionless field-effect transistor with a quad gate and multiple channels has been proposed and thoroughly simulated. The proposed device offers a lower I off current of 4.34 × 10−19 A, an I on current of 4.17 × 10−06 A with an I on/I off current ratio of 9.65 × 1012, a threshold voltage of 0.86 V, a transconductance of 5 × 10−05 S, a drain-induced barrier lowering (DIBL) of 22 mV/V, and a subthreshold slope (SS) of 61.51 mV/dec. The visual contour plots of the device are also included in this study to understand the working mechanism. The larger tunneling width between the channel drain and barrier height between the source–channel interface exhibits a lower leakage current and better performance. The performance of the proposed device is also studied when the work function between the semiconductor and gate material is altered. The work function difference improves the performance metrics. Aside from that, the effects of temperature variation on the device's performance characteristics are also being studied. When the temperature varies by 33% the threshold voltage of the proposed device drops by only 7% which shows a minimum variation in the proposed device. The results obtained from the proposed device exhibit the potential of using multi-gate multi-channel junctionless field effect transistor (MCMG) device in low-power logic circuits and memory devices.