Integrated Voltage Regulator Research Articles

Power Delivery for High-Performance Microprocessors—Challenges, Solutions, and Future Trends

The power delivery requirements for the early microprocessors were fairly rudimentary due to the relatively low power levels. However, several decades of exponential scaling powered by Moore's law have greatly increased the power requirements and the complexity of the power delivery scheme. The breakdown in Dennard scaling in the mid-2000s has ushered in the multicore era which has increased the number of cores and the power consumption in microprocessors. The steady growth in the power levels and the number of power rails in high-performance microprocessors have increased the power delivery challenges. Integrated voltage regulators (IVRs) have emerged as a key power delivery technology to address these challenges. There are a number of IVR schemes implemented on-die ranging from the simple power gate to fully integrated switching regulators. After covering the fundamentals of power delivery, this article discusses the pros and cons of different types of IVR as well as the technology ingredients required to meet future IVR requirements. This article concludes with a section on advanced packaging technologies that are being developed and needed to enable heterogeneous integration and their impact on power delivery.

Design and Characterization of Package-Embedded Solenoidal Magnetic Core Inductors for High-Frequency and High-Efficiency SIP Integrated Voltage Regulators

In this article, the design and characterization of package-embedded solenoid inductors for a high-efficiency, four-phase system-in-package (SIP) buck-type integrated voltage regulator (IVR) switching at 100 MHz is discussed. The IVR enables three conversion ratios (5, 3, and 1.7–1 V) with a minimum inductance of 25 nH/phase and a load current of 10 A (2.5 A/phase). Two inductor designs (one with a rectangular core made of an epoxy dielectric/NiZn ferrite composite magnetic material/epoxy dielectric stack and one with an elliptical core of NiZn ferrite composite magnetic material only) were optimized and compared based on the highest achievable IVR efficiency. At high-load conditions (>5 A), the elliptical core inductor showed higher efficiency than the rectangular core inductor over the frequency range investigated (10–100 MHz). The elliptical core inductors were fabricated using a novel fabrication process combining core printing, noncontact photolithography, and copper electroplating. Two simple deembedding techniques which use a single thru structure and its equivalent circuit model as well as a cascade-based two-port analysis were introduced for the characterizations of the fabricated inductors. The accuracy of these deemebedding techniques was assessed using commercial, fixed-air core inductors and standard THRU and thru–reflect–line (TRL) deembedding for comparison purpose. Less than 5% difference was observed between the TRL and the introduced deembedding techniques for the inductance and ac resistance for both the fixed air core and package-embedded magnetic core inductors. The extracted electrical parameters of the fabricated inductors were compared with the modeling results and a good correlation was observed at 100 MHz.

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities

The system-on-chip (SoC) designs for future Internet of Things (IoT) systems, spanning client platforms to cloud datacenters, need to deliver uncompromising and scalable performance with extreme energy efficiency for diverse workloads and applications, while satisfying a wide range of energy budgets, as well as platform cooling and power delivery constraints. Low-latency, burst-mode responsiveness, and scalable high-throughput performance must be delivered on demand for a range of thread-parallel, task-parallel, and data-parallel workloads covering traditional and emerging applications. This article discusses the challenges and opportunities for many-core SoC design in scaled CMOS process operating over a wide voltage-frequency range including near-threshold-voltage (NTV) that can meet the compute demands of the future at scale, flexibly, and efficiently. This article covers: 1) circuit design techniques for NTV cores; 2) mitigation techniques for within-die parameter variations via multivoltage frequency schemes; 3) digital integrated voltage regulators (VRs) for fine-grain and wide-range voltage modulation; and 4) radiation-induced soft error rate (SER) characterization and mitigation techniques to enable reliable operation at NTV. Silicon prototype examples will be used to illustrate the different techniques and highlight future research directions.

Statistical Analysis of the Efficiency of an Integrated Voltage Regulator by Means of a Machine Learning Model Coupled with Kriging Regression

This paper presents a preliminary version of a probabilistic model for the uncertainty quantification of complex electronic systems resulting from the combination of the leastsquares support vector machine (LS-SVM) and the Gaussian process (GP) regression. The proposed model, trained with a limited set of training pairs provided by a set of full-wave expensive simulations, is adopted for the prediction of the efficiency of an integrated voltage regulator (IVR) with 8 uniformly distributed random parameters. The accuracy and the feasibility of the proposed model have been investigated by comparing the model predictions and its confidence intervals with the results of a Monte Carlo (MC) full-wave simulation of the device.

Fully Integrated Switched-Inductor-Capacitor Voltage Regulator With 0.82-A/mm2 Peak Current Density and 78% Peak Power Efficiency

Fully integrated voltage regulators (FIVRs) can improve the performance and reduce the power consumption of a system-on-chip (SoC) by providing point-of-load voltage regulation with dynamic voltage scaling. The desirable attributes of FIVRs include high power efficiency, high power density, and fast transient response, which are difficult to achieve due to on-chip area constraint and parasitic effects. Low-quality and low-density on-chip inductors and capacitors are currently the main performance-limiting factors. This article presents a switched-inductor-capacitor (SIC) voltage converter that can operate more efficiently with compact on-chip air-cored metal-tracked inductors than existing step-down voltage converters. The SIC converter consists of an inductor, a flying capacitor, and three power switches, and it can provide fine-grained voltage regulation by using pulsewidth-modulation (PWM) control. The unique SIC converter topology eases the on-chip inductor integration by positioning the inductor at the input power supply and reducing the current stress of the inductor. A proof-of-concept fully integrated SIC voltage regulator is fabricated in a 65-nm CMOS process, with an area of 1.3 mm × 0.5 mm excluding pads. The output voltage can be regulated from 0.6 to 0.9 V given a 1.2-V input power supply. The output voltage ripple is below 56 mV over the entire range of output voltages and load currents. The peak power efficiency is 78% at an output of 0.9 V and 406 mA. The peak power density is 730 mW/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the peak current density is 820 mA/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A comparative study of digital low dropout regulators

Granular power management in a power-efficient system on a chip (SoC) requires multiple integrated voltage regulators with a small area, process scalability, and low supply voltage. Conventional on-chip analog low-dropout regulators (ALDOs) can hardly meet these requirements, while digital LDOs (DLDOs) are good alternatives. However, the conventional DLDO, with synchronous control, has inherently slow transient response limited by the power-speed trade-off. Meanwhile, it has a poor power supply rejection (PSR), because the fully turned-on power switches in DLDO are vulnerable to power supply ripples. In this comparative study on DLDOs, first, we compare the pros and cons between ALDO and DLDO in general. Then, we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement. Finally, we discuss the design trends and possible directions of DLDO.

Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC

Interposer-based 2.5-D integrated circuits (ICs) enable the chip-level reuse of hard intellectual properties (IPs), also known as chiplets. Such system-level integration shortens the design cycle considerably for large-scale and heterogeneous chips. Besides traditional interposers, which only provide passive elements and routing, active interposers are furthermore comprised of logic components. When implemented carefully using a dedicated electronic design automation (EDA) flow, an active interposer can significantly improve the design quality and flexibility for 2.5-D ICs. In this article, we present a complete EDA flow and design strategies targeting, such active interposer-based 2.5-D ICs. Our key contributions include the coanalysis of power, performance, signal and power integrity, and the related co-optimization of chiplets and the active interposer. Our benchmark is a 64-core RISC-V architecture, organized into multiple chiplets and interconnected by a system-level network-on-chip (NoC). For efficiency, we embed the NoC routers and integrated voltage regulators (IVRs) into the active interposer. Moreover, we integrate security monitors into the interposer-based NoC to protect the system and its shared memories against adversarial traffic. The simple yet powerful benefit of this implementation is to offer security by construction, as it is based on a clear physical separation between critical and trusted components (the system-level NoC) versus commodity components (the chiplets). We contrast our active, secured design to a passive, unsecured design baseline of the same RISC-V benchmark and find that the active design reduces the silicon area by 18.5%, power by 3.2%, and IR drop by 73.7%.

A Monolithic Resonant Switched-Capacitor Voltage Regulator With Dual-Phase Merged-LC Resonator

Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged-LC resonator, used in a resonant switched-capacitor voltage regulator. The merged-LC resonator combines flying capacitance and inductance into a single structure to reduce ac resistive losses, achieving higher efficiency and power density. The voltage regulator is implemented in a 0.18-μm CMOS process and achieves 85.5% efficiency at 0.47 W without off-chip passive components. Light-load efficiency is extended through the use of OFF-time modulation (OTM); the design achieves <; 40-mV under-/over-shoot during 2-50-mA/4-μs load transients.

Stresses modeling in multilayer semiconductor structures of automobile regulators and predicting the reliability of their operation

The problems of increasing the reliability of microelectromechanical systems are considered on the example of an automobile voltage regulator. A model of the process is proposed and a study of the effect of temperature on the formation of stress fields in semiconductor structures of active elements of the controller is carried out. The studies assumed of a possible reason for the change in the parameters of the regulator due to the appearance of defects in the crystal structure of the semiconductor material in the structures of integrated voltage regulators. For the study, a mathematical model was proposed that describes the behavior of a semiconductor element of a real car voltage regulator. It was found that the distribution of stresses in the structures is uneven and the maximum value of stresses reaches the edges., An increase in temperature gradients in the structures of regulators leads to the formation of dislocations that change the electrical characteristics of devices. As a result of modeling, it has been established that thermoelastic stresses arising in the process of manufacturing and functioning of semiconductor structures of a regulator in regulators of this type can cause a change in the structure of a semiconductor device due to relaxation of elastic stresses at dislocations. in cars. Measures are proposed, including thermostating of the sensitive elements of microelectromechanical structures, which will increase their service life.

Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD

This work studies the effect of system-level ESD on chip-level power integrity of ICs. The analysis reveals that isolating the ground nets of the various on-chip power domains impedes the cross-domain propagation of ESD-induced supply noise. Further analysis as well as circuit simulation show that an integrated voltage regulator (IVR) can provide increased immunity to ESD-induced supply noise, especially if the internally generated power supply does not utilize any PCB-level decoupling capacitors. However, the IVR’s PMOS pass transistor may discharge the internally regulated supply if the IO supply domain collapses due to ESD. Key findings of the analysis are confirmed by measurements performed on two test chips which have differing IVR designs.

Voltage-Stacked Power Delivery Systems: Reliability, Efficiency, and Power Management

In today's manycore processors, the energy loss of more than 20% may result from inherent inefficiencies of conventional power delivery system (PDS) design. By stacking multiple voltage domains in series to lower the step-down conversion ratio of the off-chip voltage regulator module (VRM) and reduce the energy loss along the path of the power delivery network (PDN), voltage stacking (VS) offers a novel alternative power delivery technique to fundamentally improve power delivery efficiency (PDE). However, VS suffers from aggravated supply voltage noise from the current imbalance, which hinders its adoption. In this article, we investigate practical VS implementation in manycore processors to improve PDE and achieve reliable performance, while maintaining compatibility with advanced power management techniques. We first present the system configuration of a voltage-stacked manycore processor. We then systematically characterize supply voltage noise in VS, identify global, and residual differential currents as its dominant contributors, and calculate the possible worst supply voltage noise. We next propose a hybrid voltage regulation solution, based on a charge-recycling off-chip voltage regulator and distributed integrated voltage regulators, to mitigate supply voltage noise effectively. We also study the compatibility of VS with higher-level power management techniques. Finally, the performance of a voltage-stacked GPU system is comprehensively evaluated. The simulation results show that our approach can achieve 93.5% PDE, reducing the power loss by 13.6% compared to conventional single-layer PDS.

A New Fan-Out-Package-Embedded Power Inductor Technology

In this letter, a fan-out-package-embedded power inductor technology is proposed. The inductor is embedded in a silicon-based fan-out package and surrounds the packaged die in which a voltage converter IC can be put. To demonstrate the integrated power inductor technology, a 2.4-nH air-core inductor for integrated voltage regulator applications is fabricated. The fabricated inductor shows a dc resistance of 5.0 $\text{m}\Omega $ and quality factors of 43–67 in the frequency range of 100–500 MHz. The small dc resistance and high quality factors make this integrated inductor technology promising for integrated power conversion.

Electrical and Thermal Characterization of an Inductor-Based ANPC-Type Buck Converter in 14 nm CMOS Technology for Microprocessor Applications

Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB and inductor-based four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1% at an output power of P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> = 640 mW and a switching frequency of f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> = 50 MHz and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> ∈ [500 mW, 600 mW]; at P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> = 890 mW, a chip current density of 24.7 A/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

Substrate-Embedded Low-Resistance Solenoid Inductors for Integrated Voltage Regulators

Integrated power conversion and delivery are the key to achieve high-efficiency and high-performance data processing. Power inductors with high power density and low dc resistance are the key enabler to realize miniaturized voltage regulators (VRs) with high efficiency. With the integrated voltage regulators (IVRs), interconnection length from the battery to the loads can be dramatically reduced, resulting in lower conduction loss and higher power efficiency. This article demonstrates substrates with embedded high-power-density solenoid inductors with an ultralow dc resistance for the IVRs. By incorporating advanced metal–polymer magnetic composites as the cores, the inductors show a high inductance density of 7 nH/mm2 with an ultralow dc resistance of 10 $\text{m}\Omega $ . With a low thickness of $ , the power inductors can be embedded into substrates and positioned close to the loads to realize the IVRs. A substrate-compatible panel-level process was developed to embed the magnetic-core inductors with high throughput and low cost. Compared with the air-core inductors, the magnetic core achieved four times improvement in inductance for the same dc resistance, indicating substantial footprint reduction and improvement in efficiency.

A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors

Fully integrated voltage regulators (FIVRs) offer many advantages, such as fine-grained power management, fast transient response, and reduced form factor. This article addresses light-load efficiency in FIVRs with nH-scale air-core inductors. The challenges of implementing efficient discontinuous conduction mode (DCM) operation at high switching frequencies are discussed, which include zero current detection, inductor ac-loss effects, and power delivery network (PDN) resonances. A prototype in 14-nm CMOS is presented, which shows the DCM operation at up to 70 MHz with a peak efficiency of 88% for 1.6–1.2-V conversion.

A Suspended Thick-Winding Inductor for Integrated Voltage Regulator Applications

In this letter, a suspended thick-winding inductor is demonstrated for integrated voltage regulator applications. A suspended thick-winding inductor with an area of 2.9 mm2 and an inductance of 25 nH is designed and fabricated. The inductor has a winding thickness of $65~\mu \text{m}$ and a DC resistance of 121 $\text{m}\Omega $ . A quality factor >30 is maintained at 100–200 MHz. A peak inductor efficiency of 97.8% is analytically calculated for voltage conversion from 1.8 V to 1.1 V at 100 MHz.

Study of Thin-Film Magnetic Inductors Applied to Integrated Voltage Regulators

Intel's microprocessors are powered by high-frequency fully-integrated switching regulators implemented on die. Current products use non-magnetic inductors designed in the package substrate. This article investigates the use of magnetic thin film inductors fabricated on silicon wafers as an alternative that improves conversion efficiency while achieving higher inductance per area density. This article builds on the earlier work done on thin film inductors at Intel, and explores the feasibility of using them in a high volume product. A number of different design variations are studied to look at tradeoffs between efficiency, saturation characteristics, transient response, and voltage ripple. This is accomplished through a combination of passive measurements using a vector network analyzer (VNA) and active measurements on a fully functioning integrated voltage regulator system.

Autotuning of Integrated Inductive Voltage Regulator Using On-Chip Delay Sensor to Tolerate Process and Passive Variations

This paper demonstrates autotuning of the coefficients of the feedback loop of an inductive integrated voltage regulator (IVR) using an on-chip delay sensor. The proposed approach improves the effective performance of the digital core under variations in the on-die/package integrated passives and transistor process. A 130-nm CMOS test-chip is designed containing a multisampled 125-MHz IVR with a wirebond inductor, on-die capacitor, and all-digital proportional-integral-differential (PID) controller powering a parallel Advanced Encryption Standard (AES) engine. The autotuning is performed using a Vernier delay line based on-chip delay sensor and an all-digital tuning engine. The measurement results demonstrate up to 5.2% improvement in the maximum operating frequency of the AES core using performance-based autotuning.

Design, Fabrication, and Characterization of Package Embedded Solenoidal Magnetic Core Inductors for High-Efficiency System-In-Package Integrated Voltage Regulators

In this paper, we discuss the design, fabrication, and characterization of package embedded solenoidal inductor using a NiZn ferrite magnetic core material based on the novel fabrication process. The process relies on stencil printing of the magnetic core material along with the photolithography and copper electroplating of the inductor’s traces. The electrical parameters of the fabricated inductors were extracted using a pi-equivalent circuit and showed an average dc resistance of 29 $\text{m}\Omega $ , an inductance of 26 nH, and an ac resistance of $2.62~\Omega $ at 100 MHz, which represents the targeted switching frequency of the system-in-package integrated voltage regulator. The organic substrate parasitic effects were accounted for through the extraction of an average shunt capacitance of 1.2 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The measured 10% saturation current of the inductor was 9.6 A. The electrical parameters of the fabricated inductors were modeled and showed a good agreement with the measured data.

Magnetic Core Solenoid Power Inductors on Organic Substrate for System-in-Package Integrated High-Frequency Voltage Regulators

In this paper, the design, modeling, fabrication, and characterization of System-in-Package (SiP) solenoid power inductor using a NiZn ferrite composite magnetic core material is demonstrated. A novel fabrication process has been developed for integrating the inductor into the buck-type integrated voltage regulator (IVR) module. The process uses stencil printing to deposit and pattern the magnetic core material. Photolithography and copper electroplating are used to form the windings. The electrical parameters of the fabricated inductors were extracted from measurements. The inductors had an average dc resistance of 19 $\text{m}\Omega $ , average inductance of 28.3 nH, and average ac resistance of $2.28~\Omega $ at 100 MHz, which is the operating frequency of the IVR. The organic substrate parasitic effect led to an average shunt capacitance of 2.31 pF and an average parasitic conductance of 0.12 mS at 100 MHz. The 10% saturation current was 11.53 A. The electrical parameters of the fabricated inductors were modeled and showed good accuracy with measured data. The inductors showed an inductance to dc resistance ratio of 1613 nH/ $\Omega $ . The area and volume energy densities were 158.4 nJ/mm2 and 283.0 nJ/mm3, respectively. These are the highest reported values for a solenoid magnetic core power inductor at 100 MHz.