Analysis and Design of Integrated Voltage Regulators for Supply Noise Rejection During System-Level ESD

Abstract

This work studies the effect of system-level ESD on chip-level power integrity of ICs. The analysis reveals that isolating the ground nets of the various on-chip power domains impedes the cross-domain propagation of ESD-induced supply noise. Further analysis as well as circuit simulation show that an integrated voltage regulator (IVR) can provide increased immunity to ESD-induced supply noise, especially if the internally generated power supply does not utilize any PCB-level decoupling capacitors. However, the IVR’s PMOS pass transistor may discharge the internally regulated supply if the IO supply domain collapses due to ESD. Key findings of the analysis are confirmed by measurements performed on two test chips which have differing IVR designs.