Tutorial 4A: Supply voltage noise and mitigation for real world SoCs

Abstract

The past decade has seen a great deal of attention and effort focused on circuits, architectures and methodologies for energy-efficient and low power computing across a broad range of applications from ultra-low power devices to high-end servers. As designers continue to seek and evaluate low power technologies to enable the next generation of computing, the traditionally unheralded problem of voltage margin minimization has emerged to become one of the most significant sources of inefficiency and dissipation. Real-world integrated systems are margined, or guard-banded to address many sources of noise and variability including process, temperature, aging, and supply voltage noise and offsets. The trend toward multiple, fine-grained voltage domains, and aggressively voltage-scaled systems has exacerbated the problem. Voltage-margin minimization is a central component of modern low power design. Indeed, many recent low power efforts in the industry have moved beyond methodology and circuit design to address voltage margin minimization! In this tutorial, I propose a modern treatment of low-power design by actively managing supply-voltage variations. In contrast with text-book approaches, I examine a blend of well-established and emerging solutions that have proven to be effective in real-world constrained systems. The tutorial is organized in two parts. In the first, I begin by analyzing the main contributors toward voltage margins, including practical sources that are related to IC test and product deployment. A subsequent discussion on the major sources of voltage-margins is followed by an examination of a variety of circuit-architecture techniques used to directly and indirectly reduce voltage supply noise margins. High-density de-cap technology, active decap, supply-resonance avoidance, operation-throttling and adaptive clocking techniques to mitigate supply voltage noise. These techniques will be presented in the context of production designs and their constraints for a system-aware treatment of the subject. In the second section, I focus on Integrated Voltage Regulation (IVR) circuits. As designers grapple with more aggressive voltage scaling in the presence of supply variation, Integrated Voltage Regulation (IVR) has emerged as the key to achieving fine spatio-temporal control of SoC supply voltages. IVR has already been deployed for energy-efficient operation in high performance systems (Intel Haswell), and the trend to incorporate IVR to support finer voltage domains continues. We examine recent developments and challenges in the area of integrated voltage regulation across the three major voltage regulator technologies: switching-inductor converters, switched-capacitor converters, and low-dropout (linear) regulators. This tutorial provides an overview of low power circuit and architecture techniques with a system-level context. It is designed to be readily accessible to graduate students and practicing engineers alike, with a blend of well-established and emerging approaches to low power design.