Chapter 3 - Low Power Design Techniques, Design Methodology, and Tools

Abstract

This chapter focuses on the design techniques that are developed to reduce power consumption. Low power technologies and techniques for energy efficiency are distinctive combinations of advanced architectural techniques and circuit design techniques with the latest design methodology. These technologies and techniques provide the highest possible performance levels within a restricted power budget. They can be applied to any application, benefiting the user by extending battery life without impacting performance as well as keeping energy costs lower. Various low power circuit and architectural techniques, for mitigating leakage power, are described in this chapter. These include power gating, dynamic process temperature control, static process compensation, state-retention power gating, clock gating, low power modes, and asynchronous circuits. Power consumption of mobile devices has moved to the forefront of SoC development concerns. Designing for low power can have a significant impact on the power budget of a mobile device. In addition, identifying and resolving power problems late in the flow requires time consuming and expensive iterations. However, designing for low power adds an additional degree of complexity to an already complex problem that has historically targeted performance and area. Optimizing the three variable equations require a new class of EDA tools that are able to address the power problem from the start to the end of the SoC design flow. In addition, comprehensive power reduction also demands a strong ecosystem that includes low power hardware IP blocks, low power libraries, modeling techniques, and silicon wafer fabrication flows that support the low power design methodology.