Threshold Voltage Instability Research Articles

Oxygen vacancy formation and the induced defect states in HfO2 and Hf-silicates – A first principles hybrid functional study

O vacancy formation and the associated electronic defect states in Hf-based oxides have been investigated over a wide range of compositions using first-principles hybrid density functional calculations. Based on the generated structure models, we have identified the most probable O coordination structures in amorphous HfO2 and in Hf-silicates, respectively. Our calculations showed that the formation energies of O vacancy and the positions of the induced defect states in the band gap are largely dependent on the local structures of the vacancy site rather than on the compositions of Hf-silicates. Considering the measured valence band offset between Si and Hf-silicates, a considerable amount of O vacancies are likely to stay in the charge neutral state in Hf-silicates when the Fermi level lies in the band gap region of Si. Furthermore, the concentration of O vacancy in Hf-silicates was found to be much lower than that in HfO2 when the Fermi level lies in/below the mid-gap region of Si. Consequently, the flat band voltage shift and the transient threshold voltage instability can be significantly reduced in Hf-silicates in comparison to that in HfO2, indicating that the presence of a Hf-silicate layer in between the gate oxides and the Si substrate could be beneficial to the performance of the CMOS device.

Characterization of VT‐instability in enhancement‐mode Al2O3‐AlGaN/GaN MIS‐HEMTs

AbstractThe threshold voltage (VT) instability of metal‐insulator‐semiconductor high electron mobility transistors (MIS‐HEMTs) is investigated. In the enhancement‐mode AlGaN/GaN MIS‐HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi‐static I ‐V (current‐voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT‐instability is attributed to the traps located at the dielectric/III‐nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi‐static measurement can only reflect slow traps (deep traps), and is more accurate for VT‐instability evaluation. In addition, the existence of bulk traps is implied by a slow time‐dependent shift of VT under large gate bias. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Charge Loss Mechanisms of Nitride-Based Charge Trap Flash Memory Devices

Technology scaling challenges for flash memory beyond 30 nm exacerbated as device fundamental limits are fast approaching. Nitride-based charge trap flash (CTF) is one of the most viable alternatives to eclipse floating gate flash in the market by leveraging the existing materials as compared with other exploratory nonvolatile memory devices. However, postcycled threshold voltage instability in the form of charge loss (CL) mechanisms remains as critical reliability challenges to further improve long-term data retention performance. This paper focuses on long-term data retention reliability issues with an emphasis on major CL mechanisms of nitride-based CTF memory. It encompasses comprehensive reviews and discussions on major CL mechanisms due to intrinsic and extrinsic causes. This paper would serve as a good reference for the future development of nitride-based CTF memory.

A new two-dimensional TCAD model for threshold instability in silicon carbide MOSFETs

Threshold voltage instability is a main reliability issue preventing the wide use of silicon carbide MOSFETs power devices. In this paper, a novel two-dimensional TCAD model based on trap-assisted tunneling is proposed to simulate quantitatively the trapping kinetics, the short/long-term degradation behavior, and the recovery in SiC MOSFETs submitted to positive gate bias stress. After calibration, the new model has been applied to a typical n-channel 4H SiC MOSFET with a 50nm thick gate oxide submitted to stress, recovery, and characterization phases. The obtained results are in excellent agreement with the experimental data reported in literature. Furthermore, the model has been shown to provide deep insight into microscopic properties and spatial charge distributions, which cannot be accessed by the existing one-dimensional theoretical models.

High temperature gate-bias and reverse-bias tests on SiC MOSFETs

As SiC MOSFET manufacturing technology continues to mature, an assessment of the stability and reliability becomes essential for the advanced development of the devices based on it. HTGB and HTRB tests are the commonly used qualification tests for discrete semiconductor devices which are performed in this work to characterise gate-oxide integrity and verify junction and termination robustness. Gate bias stress induced threshold voltage instability and leakage current degradation resulted from drain-source reverse bias stress at elevated temperature is investigated and reported.

A Two-Step Electrical Degradation Behavior in α-InGaZnO Thin-Film Transistor

In this study, we explored the threshold voltage instability behavior in amorphous indium-gallium-zinc oxide (α-IGZO) thin-film transistor (TFT). A tow-step electrical degradation behavior of α-IGZO TFT was found under gate-bias stress. A usual small positive shift followed by a special negative shift of threshold voltage is characterized in the α-IGZO TFT. We suggest that the positive shift of the threshold voltage is because of charge trapping in the gate dielectric and/or at the channel/dielectric interface, while the negative shift of threshold voltage may be attributed to electric field induced extra electron carriers from H2O molecules in the back channel protective layer.

Electric Stress-Induced Threshold Voltage Instability of Multilayer MoS2 Field Effect Transistors

We investigated the gate bias stress effects of multilayered MoS2 field effect transistors (FETs) with a back-gated configuration. The electrical stability of the MoS2 FETs can be significantly influenced by the electrical stress type, relative sweep rate, and stress time in an ambient environment. Specifically, when a positive gate bias stress was applied to the MoS2 FET, the current of the device decreased and its threshold shifted in the positive gate bias direction. In contrast, with a negative gate bias stress, the current of the device increased and the threshold shifted in the negative gate bias direction. The gate bias stress effects were enhanced when a gate bias was applied for a longer time or when a slower sweep rate was used. These phenomena can be explained by the charge trapping due to the adsorption or desorption of oxygen and/or water on the MoS2 surface with a positive or negative gate bias, respectively, under an ambient environment. This study will be helpful in understanding the electrical-stress-induced instability of the MoS2-based electronic devices and will also give insight into the design of desirable devices for electronics applications.

Photo-bias instability of metal oxide thin film transistors for advanced active matrix displays

Abstract

Comparison of the role of holes and electrons in hysteresis and threshold voltage stability of organic field effect transistors

AbstractElectrical measurements on copper phthalocyanine (CuPc)‐based organic field effect transistors using SiO2 dielectric revealed hysteresis and threshold voltage instability to be due to the combined effect of both hole‐ and electron‐trapping mechanisms, with the electron‐trap density being higher than hole‐trap density. Hysteresis was found to increase further after modifying the SiO2 surface with octadecyltrichlorosilane (OTS) while it reduced drastically after polystyrene (PS) modification. Individual contribution of holes and electrons to hysteresis and the cause of increased/reduced trapping of the same for interface modified devices were identified. The increase in hysteresis with OTS‐modified devices was attributed to increase in hole‐trap density arising from a larger grain‐boundary density of CuPc films. Minimum grain‐boundary density and efficient removal of trap centers at dielectric/semiconductor interface using PS modification resulted in minimum hysteresis. Comparison of hole‐ and electron‐trap densities estimated for measurements under different ambient conditions, like high humidity conditions and oxygen flow, showed that hole‐trap density increased with increase in humidity. Under oxygen flow, hysteresis, and hole‐trap density were found to reduce considerably, which could be attributed to creation of excess holes that readily fill hole traps, thereby resulting in increased mobile carrier concentrations.

Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Investigated transfer characteristics on threshold voltage instability behavior in amorphous indium-gallium-zinc oxide thin-film transistor (α-IGZO TFT). A two-step electrical degradation behavior of α-IGZO TFT was found under gate-bias stress. A usual small positive shift followed by a special negative shift of threshold voltage is characterized in the α-IGZO TFT device. We suggest that the positive shift of the threshold voltage is due to the charge trapping in the gate dielectric and/or at the channel/dielectric interface, while the negative shift of threshold voltage is assigned to electric field-induced extra electron carriers from H2O molecules in the back channel protective layer. We conclude that the H2O molecules and the quality of passivation layer affect the degradation behavior of α-IGZO TFT devices.

Improved Degradation and Recovery Characteristics of SiGe p-Channel Metal–Oxide–Semiconductor Field-Effect Transistors under Negative-Bias Temperature Stress

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔVth caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Effect of Stress and Measurement Conditions in Determining the Reliability of SiC Power MOSFETs

A review of the threshold-voltage instability effect in SiC MOSFETs and the issues regarding the effect of stress and measurement conditions in determining the reliability of these devices is presented. The complex response of near-interfacial oxide traps, as well as other interfacial charge, to bias and temperature with time is discussed, and how it affects the accuracy of reliability measurements. The strong dependence on measurement speed is also addressed. All these issues point to the need for a separate, appropriate reliability test standard for SiC MOSFETs, rather than using the existing standard based on Si technology.

Comparative study of electrical characteristics in (1 0 0) and (1 1 0) surface-oriented nMOSFETs with direct contact La-silicate/Si interface structure

This study reports on the electrical characteristics of (110)-oriented nMOSFETs with a direct contact La-silicate/Si interface structure and the detailed comparison with (100)-oriented nMOSFETs. Precise control of oxygen partial pressure can provide the scaled EOT down to 0.73nm on (110) orientation in common with (100) orientation. No frequency dispersion in Cgc–V characteristic for (110)-oriented nMOSFETs is successfully demonstrated at scaled EOT region, while higher amount of available bonds on (110) surface results in a larger interface state density, leading to the degradation of sub-threshold slope. High breakdown voltages of 2.85V and 2.9V for (100)- and (110)-oriented nMOSFETs are considered to be due to superior interfacial property. The electron mobility on (110) orientation is lower than that on (100) orientation because of the smaller energy split between fourfold valleys and twofold valleys as well as the larger density of states for lower-energy valleys in the (110) surface. Moreover, electron mobility is reduced with decreasing EOT in both (100)- and (110)-oriented nMOSFETs. It is found that threshold voltage instability by positive bias stress is mainly responsible for bulk trapping of electron even with a larger interface state density in (110) orientation and influence of surface orientation on threshold voltage instability is negligibly small.

Electron trapping at the high-κ/GeO2 interface: The role of bound states

Passivation of the germanium interface using native oxide results in a potential well at the interface of GeO2 and high-κ dielectric for n-channel metal-oxide-semiconductor field effect transistors. The well forms a potential trapping site for electrons, which could result in threshold voltage instability. We present calculations for the bound states and their occupancy in the well. The significance of threshold voltage shift in an 8-nm node field effect transistor and those with larger dimensions is investigated. The main conclusion is that charge storage in the well is insignificant at the 8-nm technology node but can have a significant effect on larger devices.

Bound states within the notch of the HfO2/GeO2/Ge stack

A model is presented to allow calculation of the bound states in the conduction band notch at the interface between the interfacial native GeO2 and high-κ dielectric layer in a Ge MOSFET gate stack. The notch represents a potential charge trapping site, which can induce threshold voltage instability. The model is applied to a three-dimensional structure, and the number of electrons or average occupancy of confined electrons in the notch is calculated. The effect of device physical and electrical parameters on the number of bound states and average occupancy of states in the notch is discussed. The significance of the confined charge in the notch and its effect on the threshold voltage shift in an 8-nm node Ge MOSFET is investigated. The main conclusion is that charge storage in this notch is insignificant at the relevant technology node.

Electrical Properties of MOS Structures on 4H-SiC (11-20) Face

Threshold voltage (VTH) instability, channel mobility and oxide reliability have been investigated for meta-oxide-semiconductor (MOS) structures on 4H-SiC (11-20) face using various gate oxidation procedures. Channel mobility of n-channel MOSFET with a gate oxide by pyrogenic oxidation is higher than that by dilute-DRY oxidation followed by a nitrous oxide (N2O) post-oxidation annealing (POA). On the other hand, oxide reliability for the pyrogenic oxides is poor compared with the dilute-DRY/N2O oxides. A Hydrogen POA is effective in an improvement of channel mobility for both oxides, but causes a harmful effect on VTH stability. Temperature dependence of VTH instability indicates that MOS structure grown by dilute-DRY followed by N2O POA is suitable for a practical use of SiC MOS power devices.

Evaluation of PBTS and NBTS in SiC MOS Using <i>In Situ</i> Charge Pumping Measurements

Since power devices such as DMOSFETs will operate at higher temperatures with accelerated degradation mechanisms, it is essential to understand the effects of typical operating conditions for power electronics applications. We have found that SiC MOSFETs when gate-biased at 150 °C show an increasing charge pumping current over time, suggesting that interface traps (or perhaps near-interface oxide traps) are being created under these conditions. This trapping increase occurs slightly above linear-with-log-time and mimics previously observed threshold voltage instabilities, though a causal relationship has not yet been determined. We found the charge trapping after 104 s of BTS increased at a rate of 1x1011 cm-2/dec for NBTS (-3 MV/cm), 0.7x1011 cm-2/dec for PBTS (3 MV/cm), and 0.3x1011 cm-2/dec when grounded. The observed increase in charge trapping has negative implications for the long term stability and reliability of SiC MOS devices under operating conditions.

A Study of High Temperature DC and AC Gate Stressing on the Performance and Reliability of Power SiC MOSFETs

Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.

Investigation of threshold voltage instability induced by gate bias stress in ZnO nanowire field effect transistors

We investigated the threshold voltage instability induced by gate bias (VG) stress in ZnO nanowire (NW) field effect transistors (FETs). By increasing the VG sweep ranges and repeatedly measuring the electrical characteristics of the ZnO NW FETs, the VG stress was produced in the dielectric layer underneath the ZnO NW. Consequently, the electrical conductance of the ZnO NW FETs decreased, and the threshold voltage shifted towards the positive VG direction. This threshold voltage instability induced by the VG stress is associated with the trapping of charges in the interface trap sites located in the ZnO NW–dielectric interface. Our study will be helpful for understanding the stability of ZnO NW FETs during repetitive operations.

Amorphous InGaZnO Thin-Film Transistors—Part I: Complete Extraction of Density of States Over the Full Subband-Gap Energy Range

A combination of the multifrequency <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$C$</tex></formula> – <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V$</tex></formula> and the generation–recombination current spectroscopy is proposed for a complete extraction of density of states (DOS) in amorphous InGaZnO thin-film transistors (a-IGZO TFTs) over the full subband-gap energy range <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(E_{V}\leq E\leq E_{C})$</tex> </formula> including the interface trap density between the gate oxide and the a-IGZO active layer. In particular, our result on the separate extraction of acceptor- and donor-like DOS is noticeable for a systematic design of amorphous oxide semiconductor TFTs because the former determines their dc characteristics and the latter does their threshold voltage <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(V_{T})$</tex></formula> instability under practical operation conditions. The proposed approach can be used to optimize the fabrication process of thin-film materials with high mobility and stability for mass-production-level amorphous oxide semiconductor TFTs.