Threshold Voltage Instability Research Articles

ALD gate dielectrics for improved threshold voltage stability in AlGaN/GaN MOS-HFETs for power applications

Dielectrics by atomic layer deposition (ALD) are sought after for fabricating AlGaN/GaN based metal oxide semiconductor heterojunction field effect transistors (MOS-HFETs) for power applications. The ideal gate dielectric is required to suppress gate leakage and minimize threshold voltage (VT) instability by hosting minimal interface traps. Additionally, with the need for an enhancement mode device, it is preferable if it minimizes VT shift in the negative direction. For the first time, we compare popular ALD dielectrics like SiO2, Al2O3, HfO2 and HfAlO with identical electrical thickness on AlGaN/GaN, thereby ensuring identical electrostatic conditions across different dielectrics. High-k ALD dielectrics (HfAlO, HfO2 and Al2O3) are found to suppress gate leakage but host a high density of interface traps with AlGaN, thereby resulting in significant VT instability. ALD SiO2 gate dielectric, annealed in N2 above 600 °C, is a promising gate dielectric candidate which provides the most stable and least negative shift in VT while also substantially suppressing gate leakage below that of an HFET.

Investigating Effect of Postannealing Time on Positive Bias Stress Stability of In–Ga–Zn–O TFT by Conductance Method

The conductance method was used to investigate the positive bias stress (PBS) degradation mechanism of In–Ga–Zn–O (IGZO) thin-film transistor (TFT). The effects of postannealing time on the PBS degradation mechanism were investigated. The stabilization of the donorlike interface defects was found to be the reason for the threshold voltage instability in the IGZO-TFT under the PBS test. The donorlike defects at the front channel interface and in the plasma-enhanced chemical vapor deposition (PE-CVD) SiO x acted as the electron trapping centers. The electron trapping resistance of the PE-CVD SiO x was improved by increasing the postannealing time, resulting in an improvement in the PBS stability. However, long-time postannealing-induced creation of the deep acceptorlike interface defects in the TFT under the PBS. The energy distribution of the created deep acceptorlike interface defects was revealed using the conductance measurement.

Fast transient charging behavior of HfInZnO thin-film transistor

Threshold voltage instabilities and mobility degradation of amorphous oxide-based thin-film transistors (TFTs) are associated with charging phenomena in gate dielectrics, interfaces. The wide range of charge trapping when using DC techniques may mislead to the evaluation of intrinsic device characteristics. In this investigation, we studied the charging behavior in HfInZnO TFTs with the Hf metal content by fast and transient current measurement methods. Since the charge-trapping effect is negligible during fast voltage ramping, the drain current measured by the fast I−V method was higher than that obtained from DC measurement, indicating that conventional DC measurement underestimates the mobility values even for oxide-TFTs. The mobility values of the HfInZnO TFTs with high and low Hf contents were measured by the fast I–V method to be 2.7 and 13.5 cm2/V s, respectively, which were increased by 16–68% after the fast I−V measurement. In addition, trapping time constants of 24 and 17 μs for both devices were estimated by the transient I−V method. According to the fitting model, the charge trapping was governed by multiple processes with two different time constants.

Negative bias-and-temperature stress-assisted activation of oxygen-vacancy hole traps in 4H-silicon carbide metal-oxide-semiconductor field-effect transistors

We use hybrid-functional density functional theory-based Charge Transition Levels (CTLs) to study the electrical activity of near-interfacial oxygen vacancies located in the oxide side of 4H-Silicon Carbide (4H-SiC) power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). Based on the “amorphousness” of their local atomic environment, oxygen vacancies are shown to introduce their CTLs either within (permanently electrically active) or outside of (electrically inactive) the 4H-SiC bandgap. The “permanently electrically active” centers are likely to cause threshold voltage (Vth) instability at room temperature. On the other hand, we show that the “electrically inactive” defects could be transformed into various “electrically active” configurations under simultaneous application of negative bias and high temperature stresses. Based on this observation, we present a model for plausible oxygen vacancy defects that could be responsible for the recently observed excessive worsening of Vth instability in 4H-SiC power MOSFETs under high temperature-and-gate bias stress. This model could also explain the recent electrically detected magnetic resonance observations in 4H-SiC MOSFETs.

(Invited) Threshold Voltage Stability Comparison of Commercial SiC Mosfets and Related Issues

Silicon-Carbide (SiC) MOSFETs are beginning to gain wide acceptance for power electronics applications requiring high efficiency and high operational temperatures. There is a growing number of commercial offerings at 1200 V from different manufacturers that may have very distinctive processes that need to be evaluated in a consistent manner to make valid comparisons. As SiC MOSFET technology continues to mature, device performance and reliability should also improve. In recent years, a diverse number of publications in the literature have addressed the poor quality of the MOS gate dielectric layer, and the challenges related to charging of both interface defects and near-interfacial oxide defects during electrical and thermal stressing. A significant number of intrinsic defects in the gate oxide result from growth of the dielectric layer itself. Subsequent process steps can activate a number of these defects which can trap charge during electrical gate-stress, thereby altering the device threshold voltage. During bias temperature stressing, activation of additional oxide defects can occur, which gives rise to larger threshold voltage instabilities. The stability of the MOS threshold voltage under electrical gate-stress at high temperature is an important reliability phenomenon with potential application relevance. A large positive shift reduces on-state conduction, increases power losses, and may reduce efficiency in switch-mode converter applications. A large negative shift in the threshold voltage is a more serious reliability concern because of excessive drain leakage current in the MOS-channel during the off-state. This effect will limit blocking capability and possibly lead to device failure. This work will provide an overview of threshold voltage stability issues in commercially-available SiC MOSFETs subject to both positive and negative gate-stress at high temperature. Figure 1 is a plot of the subthreshold-voltage shift as a function of unipolar (positive) bias stress time for commercial devices purchased between 2012 and 2015. Recent devices show significant improvement in threshold voltage shift for a +25 V gate-bias stress at 175 °C. The older commercial devices shift considerably more, with the onset of degradation occurring much earlier in time. We have also observed differences in the responses of devices from different manufactures for similar stress and test conditions. It is expected that process differences among device manufacturers would in turn, result in differences in the bias-temperature-stress responses. A fuller discussion of these test results and related issues will be presented in the final paper. Figure 1

Exact Characterization of Threshold Voltage Instability in 4H-SiC MOSFETs by Non-Relaxation Method

In this work, we investigated the methods that measure the threshold voltage (Vth) instability without relaxation of the gate stress during the Vth measurement. We propose a non-relaxation method that demonstrates exact Vth shifts compared with conventional methods that are not as accurate. In the non-relaxation method, the constant gate-source voltage (Vgs) is continuously applied as a gate stress while the drain voltage (Vds) shift required to maintain a constant drain current (Id) is measured. Then, the Vds shift is converted to a Vth shift. The Vth shift values measured by the non-relaxation method are larger than those measured by the other methods, which means that the non-relaxation method can very accurately measure the Vth shift.

Influence of active layer thickness on contribution of hole and electron trapping to threshold voltage instability in organic field effect transistors

Effect of active layer thickness on threshold voltage stability was studied. Threshold voltage instability was found to be minimum for an optimum thickness of 15nm when operated under normal room light conditions. Influence of active layer thickness on individual contribution of hole and electron trapping effect to hysteresis was estimated. Hole and electron trap concentrations were found to exhibit different pattern of variation with thickness compared to each other. Film with 15nm thickness exhibited minimum hole trapping and maximum electron trapping effect. This could be attributed to reduced grain boundary density and availability of large photogenerated carrier concentration at the dielectric/semiconductor interface. Along with electron trap, hole trap concentrations were also shown to be significantly influenced by photogenerated carrier concentration at the interface. For further increase in thickness, increase in hole trapping and reduction in electron trapping were observed again. This could be attributed to (a) increase in grain boundary density due to volume effect and (b) lesser number of photogenerated carriers at the interface due to limitations in exciton quenching length. Hole and electron trapping effect were suggested to be mutually affecting each other, depending on active layer thickness. Effect of active layer thickness was further confirmed with frequency and voltage dependent capacitance measurements.

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity.

Compact model for parametric instability under arbitrary stress waveform

A deterministic compact model of the parametric instability of elementary devices is further developed. The model addresses the device instability class that can be traced back to microscopic reactions obeying reversible first-order kinetics. It can describe the response to any periodic stimulus waveform and it is suitable for the implementation in commercial electronic circuit simulators (Eldo UDRM). The methodology is applied to model the negative-bias-temperature threshold voltage instability of a p-channel MOSFET. A simple circuital example is shown where the simulation of threshold voltage recovery is crucial for circuit design.

Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories

This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations.

P‐20: The Effect of Oxide‐TFT Design on Voltage‐Threshold Shift

The threshold voltage (Vth) instability of oxide TFT is the largest hindrance to mass production. Stability improvement mainly focuses on the material and the process adjustment. Results in this study show that reasonable designs (such as floating SD, IGZO separation, etc.)reduce Vth shift. The influence mechanism of TFT shape to Vth shift is discussed in this paper.

Transparent Semiconducting Oxide Technology for Touch Free Interactive Flexible Displays

Amorphous oxide semiconductor thin film transistors and sensors constitute fundamental building blocks for a new generation of applications ranging from interactive displays and imaging to future electronic systems that are unconstrained by form factor. This makes the quest for high mobility materials processed at low temperatures even more compelling, to enable the layering of circuits and systems on plastic and possibly even paper substrates. Transparency is also an attractive feature that enables seamless embedding of electronics for the immersive ambient. This paper reviews the current status of the ubiquitous oxide semiconductor technology for flexible and transparent interactive displays, along with demonstrated examples of continuous thin film and nanowire systems for the transistor and sensor. Issues related to photo-sensing and active matrix operation are discussed along with solutions addressing the problem of threshold voltage instability and its compensation for fast recovery, particularly after light stress. Physics-based compact models for expedient design and simulation of analog and digital circuits are reviewed along with examples of key system building blocks. Finally we attempt to conceptualize a thin film transistor (TFT)-based fully heterogeneously integrated and autonomous system that can be realized using a combination of oxide and other technological routes.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs

A review of the basic mechanisms affecting the stability of the threshold voltage in response to a bias-temperature stress is presented in terms of the charging and activation of near-interfacial oxide traps. An activation energy of approximately 1.1 eV was calculated based on new experimental results. Implications of these factors, including the recovery of some bias-temperature stress-activated defects, for improved device reliability testing are discussed.

A Light-induced Threshold Voltage Instability Based on a Negative-U Center in a-IGZO TFTs with Different Oxygen Flow Rates

A Light-induced Threshold Voltage Instability Based on a Negative-U Center in a-IGZO TFTs with Different Oxygen Flow Rates

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Design of step composition gradient thin film transistor channel layers grown by atomic layer deposition

In this study, we proposed the artificially designed channel structure in oxide thin-film transistors (TFTs) called a “step-composition gradient channel.” We demonstrated Al step-composition gradient Al-Zn-O (AZO) channel structures consisting of three AZO layers with different Al contents. The effects of stacking sequence in the step-composition gradient channel on performance and electrical stability of bottom-gate TFT devices were investigated with two channels of inverse stacking order (ascending/descending step-composition). The TFT with ascending step-composition channel structure (5 → 10 → 14 at. % Al composition) showed relatively negative threshold voltage (−3.7 V) and good instability characteristics with a reduced threshold voltage shift (Δ 1.4 V), which was related to the alignment of the conduction band off-set within the channel layer depending on the Al contents. Finally, the reduced Al composition in the initial layer of ascending step-composition channel resulted in the best field effect mobility of 4.5 cm2/V s. We presented a unique active layer of the “step-composition gradient channel” in the oxide TFTs and explained the mechanism of adequate channel design.

Mechanisms of thermally induced threshold voltage instability in GaN-based heterojunction transistors

In this work, we attempt to reveal the underlying mechanisms of divergent VTH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows “deeper” interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices.

Structure, bonding, and passivation of single carbon-related oxide hole traps near 4H-SiC/SiO2 interfaces

Single carbon interstitial in silicon dioxide, existing in carboxyl configuration, is shown to act as a border hole trap near 4H-SiC/SiO2 interface. Using density functional theory-based formation energy considerations, it is found to switch charge state between +2 and neutral as the 4H-SiC Fermi level sweeps its charge transition level located 1.4 eV above 4H-SiC valence band edge. Thus, carboxyl defect is predicted to be a potential candidate for threshold voltage instability in 4H-SiC MOSFETs. Post oxidation annealing of the interface with nitric oxide is shown to remove carboxyl defects. However, treating the defect in H2 creates a hole trap level at 1.1 eV above 4H-SiC valence band edge similar to the original carboxyl defect. The stability of carboxyl and H2 treated carboxyl defects in their doubly positive state is explained on the basis of their structural and bonding transformations during hole capture. These include puckering and back-bonding of silicon with lattice oxygen as in the well-known oxygen vacancy (E′ center) hole traps and an increase in the bond order between carboxyl carbon and oxygen.

Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors

The conduction mechanisms and trapping effects at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors (MOSFETs) were studied by Fowler-Nordheim (FN) tunnelling and frequency dependent conductance measurements. In particular, the analysis of both MOS capacitors and MOSFETs fabricated on the same wafer revealed an anomalous FN behavior on p-type implanted SiC/SiO2 interfaces. The observed FN instability upon subsequent voltage sweeps was correlated to the charge-discharge of hole trap states close the valence band edge of 4H-SiC. The charge-discharge of these traps also explained the recoverable threshold voltage instability observed in lateral MOSFETs.