Threshold Voltage Instability Research Articles

Impact of MoS2 layer transfer on electrostatics of MoS2/SiO2 interface

Using internal photoemission of electrons from few-monolayer thin MoS2 films into SiO2 we found that the MoS2 layer transfer processing perturbs electroneutrality of the interface, leading to an increase of the electron barrier height by ≈0.5–1 eV as compared to the case of the same films synthesized directly on SiO2. This effect is associated with the formation of an interface dipole, tentatively ascribed to interaction of H2O molecules with the SiO2 surface resulting in the incorporation of silanol (SiOH) groups. This violation of the interface electroneutrality may account for additional electron scattering in ultrathin transferred films and threshold voltage instabilities. Post-transfer annealing in H2S is shown to reduce the transfer-induced interface degradation.

Understanding PBTI in Replacement Metal Gate Ge n-Channel FETs With Ultrathin Al2O3 and GeO<italic>x</italic> ILs Using Ultrafast Charge Trap–Detrap Techniques

We report positive bias temperature instability data in replacement metal gate Ge n-channel metal–oxide–semiconductor field-effect transistors with an in-situ gate stack employing an ultrathin (5 A), stable Al2O3 interlayer (IL) using ultrafast (~microseconds) characterization techniques that ensure recovery artifact-free measurements. Comparison with state-of-the-art GeO x IL is also reported besides establishing correlations between band-edge interface trap density ( ${D}_{\text {it}}$ ), mobility ( $\mu$ ), and threshold voltage ( ${V}_{T}$ ) instability. Ultrafast measure-stress-measure (UF-MSM), ultrafast measure-stress-detrap-measure (UF-MSDM), stress-induced-leakage-current (SILC), direct-current current–voltage (DCIV), split capacitance–voltage ( ${C}$ – ${V}$ ), and low-temperature full conductance techniques along with a compact model demonstrate that: 1) trap generation occurs at IL/high- ${k}$ interface during stress; 2) an increase in $\mu$ with reduction in ${D}_{\text {it}}$ does not guarantee better reliability, i.e., ${V}_{T}$ shift and $\mu$ are uncorrelated due to their dependence on separate regions of the gate stack; 3) contributions to total ${V}_{\text {T}}$ degradation from trapping and generated traps are mutually exclusive; 4) UF-MSDM is a powerful tool to estimate trap generation; and 5) ${V}_{T}$ degradation is directly proportional to high- ${k}$ thickness, varies inversely with IL thickness, and reduces with annealing.

Threshold voltage instability in SiC MOSFETs as a consequence of current conduction in their body diode

An antiparallel PiN diode is present in the structure of the SiC Power MOSFET. For simplicity, increased module current ratings, and cost reasons, it sometimes may be preferable to use this diode rather than to add an external Schottky diode to the MOSFET. However, SiC PiN diodes are sensitive to defects in the SiC crystal, and their performance can degrade rapidly.In this paper, we assess the effect of several stresses on the characteristics of a SiC MOSFET, focusing on the stresses which involve the body diode. We demonstrate that using the body diode does not degrade its performances. However, it may produce a noticeable shift in the threshold voltage of the MOSFET. While this behaviour is observed for MOSFETs from one manufacturer, it is not exhibited for others, which indicates that it may be a consequence of some particular design or manufacturing parameters.

Robust SiNx/GaN MIS-HEMTs With Crystalline Interfacial Layer Using Hollow Cathode PEALD

In this letter, we report gallium nitride-based metal-insulator-semiconductor high-electron-mobility transistors (GaN MIS-HEMTs) with a 16-nm-thick silicon nitride (SiN x ) gate insulator and surface passivation layer grown using low-temperature (300 °C) hollow cathode plasma-enhanced atomic layer deposition. Tris(dimethylamino) silane and a remote N2 plasma were used as the silicon precursor and the nitrogen co-reactant, respectively. Though the growth temperature was as low as 300 °C, we obtained excellent film properties such as a high refractive index (2.00), a high film density (2.9 g/cm3), and a low wet etch rate (0.8 nm/min) in 100:1 hydrofluoric acid. High-resolution transmission electron microscopy images of the gate stacks showed ~1.5 nm $\beta $ -phase Si3N4 crystalline interfacial layer on the GaN surface. The devices showed a negligible hysteresis of ~50 mV, a steep subthreshold slope of 76 mV/dec, and a high ON/OFF drain current ratio of ~109. In addition, the devices showed a small positive/negative bias temperature threshold voltage ( ${V}_{\text {th}}$ ) instability ( $\Delta {V}_{\text {th}}\le 0.2$ V at 25 °C and 150 °C) as well as a mitigated current collapse under an off-state quiescent ${V}_{\text {DS}}$ of 20 V.

Electronic Structure of Tantalum Oxide with Oxygen Vacancy and Polyvacancy, Oxygen Interstitial, Tantalum Interstitial and Tantalum Substituting Oxygen

The electronic properties of Ta2O5 are limited by its defects. The defects are problem if Ta2O5 is used in DRAM or as a blocking layer in a flash charge trapping memory (CTM), because it leads to a high conductivity via the traps and the threshold voltage instability. On the contrary, the high defects concentration opens the possibility of using Ta2O5 as a storage medium in the CTM [1] and resistive random-access memory (ReRAM) [2]. The aim of the study is the investigation of the electronic structure of O vacancy (VO), O polyvacancy, interstitial O and Ta atoms, O-to-Ta substitution in Ta2O5 to clarify the trap nature responsible for the charge localization and transport. The simulations carried out for the λ-Ta2O5 [3] 168-atom supercell in terms of the DFT in Quantum-ESPRESSO code. The calculated bandgap of λ-Ta2O5 is 4.2 eV. All types of native defects, except for the O interstitial, form defect states into the λ-Ta2O5 bandgap. The value of trap thermal ionization energy 0.5 eV are comparable to the experimental ones 0.7-0.8 eV [4], and optical trap energy 0.9 eV for the VO indicate that the VO in Ta2O5 can act as the charge trap, and participate in charge transport. The width of density of states defect peaks indicate the charge localization in space. The electron localization on the VO in Ta2O5 is due to the polaronic effect. The negative charge distributed between the nearest Ta atoms and it reflects the bonding character of the Ta orbitals charge density. Its allows us to conclude that the chains of closely located oxygen vacancies in TaOx can act as a conductive shunt and participate in the resistive switching. Each subsequent O vacancy forms near the already existing one, and no more than 2 removed O atoms, related to Ta atom. The O polyvacancy forms a filled defective band in Ta2O5 bandgap. The work is supported by the Russian Science Foundation grant #17-72-10103. [1] K. Hota, F.H. Alshammari, K. N. Salama et. al, Acs. Appl. Mater. Inter. 9, 21856 (2017). [2] M. Kim, S.R. Lee, S. Kim, M. Chang et. al, Adv. Funct. Mater. 25, 1527 (2015). [3] H. Lee, J. Kim, S.J. Kim et. al, Phys. Rev. Lett. 110, 235502 (2013). [4] V. Egorov, D.S. Kuzmichev, P.S. Chizhov et. al, Acs. Appl. Mater. Inter. 9, 13286 (2017). Figure 1

Trapping Effects in Si -Doped -Ga2O3 MESFETs on an Fe-Doped -Ga2O3 Substrate

Threshold voltage instability was observed on $\beta $ -Ga2O3 transistors using double-pulsed current–voltage and constant drain current deep level transient spectroscopy (DLTS) measurements. A total instability of 0.78 V was attributed to two distinct trap levels, at ${E}_{C}$ -0.70 and ${E}_{C}$ -0.77 eV, which need to be mitigated for future applications. The traps are likely located near the gate–drain edge and below the delta-doped layer, which is determined through the DLTS technique and an understanding of the fill and empty biasing conditions. The trap modulation was consistent with a gate leakage-based trap filling mechanism, which was demonstrated. It is likely that Fe is playing a role in the observed dispersion due to the close proximity of the Fe substrate.

Comparison of trapped charges and hysteresis behavior in hBN encapsulated single MoS2 flake based field effect transistors on SiO2 and hBN substrates

Molybdenum disulfide (MoS2) based field effect transistors (FETs) are of considerable interest in electronic and opto-electronic applications but often have large hysteresis and threshold voltage instabilities. In this study, by using advanced transfer techniques, hexagonal boron nitride (hBN) encapsulated FETs based on a single, homogeneous and atomic-thin MoS2 flake are fabricated on hBN and SiO2 substrates. This allows for a better and a precise comparison between the charge traps at the semiconductor-dielectric interfaces at MoS2−SiO2 and hBN interfaces. The impact of ambient environment and entities on hysteresis is minimized by encapsulating the active MoS2 layer with a single hBN on both the devices. The device to device variations induced by different MoS2 layer is also eliminated by employing a single MoS2 layer for fabricating both devices. After eliminating these additional factors which induce variation in the device characteristics, it is found from the measurements that the trapped charge density is reduced to 1.9 × 1011 cm−2 on hBN substrate as compared to 1.1 × 1012 cm−2 on SiO2 substrate. Further, reduced hysteresis and stable threshold voltage are observed on hBN substrate and their dependence on gate sweep rate, sweep range, and gate stress is also studied. This precise comparison between encapsulated devices on SiO2 and hBN substrates further demonstrate the requirement of hBN substrate and encapsulation for improved and stable performance of MoS2 FETs.

Improved Threshold Voltage Instability in 4H-SiC MOSFETs with Atomic Layer Deposited SiO<sub>2</sub>

This study reports the electrical characteristics and reliability of the atomic layer deposited SiO2 on the 4H-SiC substrate. By controlling the thickness of SiO2 in each ALD cycle, improved device properties like mobility and gate leakage were obtained as compared to the single deposition. Moreover, the optimized process dramatically reduces the threshold voltage shift under positive and negative bias stresses. This improvement can be attributed to the effective removal of unreacted metal-organic precursors, active traps, and broken bonds in the ALD SiO2 dielectrics as well as reduction in interface state density at SiC/SiO2 interface.

Review of dynamic effects and reliability of depletion and enhancement GaN HEMTs for power switching applications

GaN-based transistors are promising devices for power switching applications, but their unique properties require careful design of the circuit in order to achieve the best performance and reliability. The first part will focus on the characterisation of deep-level effects in enhancement- and depletion-mode HEMTs, which limit the performance of the transistor. Threshold voltage instabilities in MIS-HEMT structures, caused by charge trapping under the gate, and their dependence on SiN acting as the gate dielectric will be reviewed. ON-resistance increase, caused by charge trapping in the gate-drain access region, will then be discussed in normally off gate injection transistors, as well as the effect of the switching frequency on the trapping-de-trapping equilibrium condition. The second part of the paper will discuss possible failure modes related to operating conditions, starting with the oxidation of the surface and the inverse piezoelectric effect at high gate-drain voltage. To have a complete picture of high-field effects, the gate dielectric and passivation robustness will be investigated. Time-dependent degradation will then be analysed in both gate reverse and forward-bias conditions. Finally, failures related to off-state stress and to power dissipation and electric field during an ESD event in AlGaN/GaN-HEMTs will be discussed.

Quantitative analysis of charge trapping and classification of sub-gap states in MoS2 TFT by pulse I–V method

The threshold voltage instabilities and huge hysteresis of MoS2 thin film transistors (TFTs) have raised concerns about their practical applicability in next-generation switching devices. These behaviors are associated with charge trapping, which stems from tunneling to the adjacent trap site, interfacial redox reaction and interface and/or bulk trap states. In this report, we present quantitative analysis on the electron charge trapping mechanism of MoS2 TFT by fast pulse I–V method and the space charge limited current (SCLC) measurement. By adopting the fast pulse I–V method, we were able to obtain effective mobility. In addition, the origin of the trap states was identified by disassembling the sub-gap states into interface trap and bulk trap states by simple extraction analysis. These measurement methods and analyses enable not only quantitative extraction of various traps but also an understanding of the charge transport mechanism in MoS2 TFTs. The fast I–V data and SCLC data obtained under various measurement temperatures and ambient show that electron transport to neighboring trap sites by tunneling is the main charge trapping mechanism in thin-MoS2 TFTs. This implies that interfacial traps account for most of the total sub-gap states while the bulk trap contribution is negligible, at approximately 0.40% and 0.26% in air and vacuum ambient, respectively. Thus, control of the interface trap states is crucial to further improve the performance of devices with thin channels.

Improvement of Threshold Voltage Reliability of 4H-SiC MOSFETs With Lanthanum Silicate by High Temperature Forming Gas Anneal

We report the effect of a high-temperature forming gas anneal (FGA) on the electrical characteristics and threshold voltage (VT) instability of high-mobility Si-face (0001) 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) with lanthanum silicate (LaSiOx). The MOSFET with LaSiOx after 800 °C FGA in 5% H2 and 95% N2 mixture shows significantly reduced VT shift under 3-MV/cm positive bias stressing from 2.78 to 1.65 V, while maintaining high field-effect mobility of 122.7 cm2/Vs and sufficiently positive VT of 2.76 V.

A review of pulsed NBTI in P-channel power VDMOSFETs

Negative bias temperature instability (NBTI) is a phenomenon commonly observed in p-channel metal-oxide-semiconductor (MOS) devices simultaneously exposed to negative gate voltage and elevated temperature. In this study we provide overview of threshold voltage instabilities observed in commercial p-channel power vertical double-diffused MOS field-effect transistors (VDMOSFET) IRF9520 under the pulsed NBT stress conditions. These instabilities are caused by the NBT stress induced changes in oxide trapped charge and interface trap densities, and are more significant at higher voltages and/or temperatures. NBT stress induced degradation under the pulsed gate bias conditions is generally lower as compared to static stress. Less significant degradation of threshold voltage found after pulsed bias stressing is ascribed to the recovery effects. Partial recovery occurs during the low level of pulsed gate voltage as a consequence of the removal of recoverable component of degradation and is associated with passivation/neutralization of shallow oxide traps that have not been transformed into the deeper traps (permanent component). A specific approach has been applied in this study in order to assess the recoverable and permanent components of degradation in commercial p-channel power VDMOSFETs subjected to NBT stressing. Experimental data have been analysed in terms of the mechanisms responsible for changes in the densities of gate oxide charge and interface traps.

Evolution of Defect Structures and Deep Subgap States during Annealing of Amorphous In-Ga-Zn Oxide for Thin-Film Transistors

Amorphous indium gallium zinc oxide ($a$-IGZO) has drawn considerable interest as a channel material in flexible thin-film transistors (TFTs), to replace amorphous-Si-based TFTs, but $a$-IGZO-based TFTs show environment-dependent instability in threshold voltage. Investigating the variation of defect structures and subgap states with post-annealing temperature, this study reveals that the excess oxygen atoms surrounding cations or cation-vacancy-related defect clusters give rise to the instability. These results open a route to understanding the physical origin of device instability, and offer a feasible approach to tailoring such defects for practical applications.

VTH Instability of p-GaN Gate HEMTs under Static and Dynamic Gate Stress

The impacts of static and dynamic gate stress on the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> ) instability in Schottky-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shifts negatively under large positive bias static stress ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {G}}\_ {\text {stress}} &gt; 5$ </tex-math></inline-formula> V) by adopting conventional quasi-static characterization techniques. In contrast, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN layer, which is floating in the Schottky-type <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -GaN gate HEMT.

Disorder induced gap states as a cause of threshold voltage instabilities in Al2O3/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

We proposed that the disorder induced gap states (DIGS) can be responsible for the threshold voltage (Vth) instability in Al2O3/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors. In order to verify this hypothesis, we performed the theoretical calculations of the capacitance voltage (C-V) curves for the Al2O3/AlGaN/GaN structures using the DIGS model and compared them with measured ones. We found that the experimental C-V curves with a complex hysteresis behavior varied with the maximum forward bias and the sweeping rate can be well reproduced theoretically by assuming a particular distribution in energy and space of the DIGS continuum near the Al2O3/AlGaN interface, i.e., a U-shaped energy density distribution and exponential depth decay from the interface into Al2O3 layer (up to 4 nm), as well as suitable DIGS capture cross sections (the order of magnitude of 10−15 cm2). Finally, we showed that the DIGS model can also explain the negative bias induced threshold voltage instability. We believe that these results should be critical for the successful development of the passivation techniques, which allows to minimize the Vth instability related effects.

Positive and negative threshold voltage instabilities in GaN-based transistors

This paper reviews the main mechanisms responsible for bias-temperature instability (BTI) in GaN-based high electron mobility transistors. In the first part of the article, we focus on the threshold voltage instabilities of GaN-based MIS-HEMTs submitted to positive and negative gate bias. We demonstrate that the shift in threshold voltage originates from the trapping/de-trapping of defects located at the insulator/semiconductor interface and/or in the bulk dielectric. In the second part of the paper, we describe the threshold voltage instabilities of GaN-transistors with p-GaN gate, designed specifically for normally-off operation. We present original data indicating that under positive gate bias these devices with p-GaN gate may show a negative threshold voltage shift, which is fully recoverable. This effect is ascribed to the injection of holes under the gate contact, and to the corresponding accumulation of positive charge, possibly at the p-GaN/AlGaN interface.The results described within this paper provide an up-to-date description of the most relevant trapping processes that impact on the stability of threshold voltage and on-resistance in GaN-based transistors.

Reversible hysteresis inversion in MoS2 field effect transistors

The origin of threshold voltage instability with gate voltage in MoS2 transistors is poorly understood but critical for device reliability and performance. Reversibility of the temperature dependence of hysteresis and its inversion with temperature in MoS2 transistors has not been demonstrated. In this work, we delineate two independent mechanisms responsible for thermally assisted hysteresis inversion in gate transfer characteristics of contact resistance-independent multilayer MoS2 transistors. Variable temperature hysteresis measurements were performed on gated four-terminal van der Pauw and two-terminal devices of MoS2 on SiO2. Additional hysteresis measurements on suspended (~100 nm air gap between MoS2 and SiO2) transistors and under different ambient conditions (vacuum/nitrogen) were used to further isolate the mechanisms. Clockwise hysteresis at room temperature (300 K) that decreases with increasing temperature is shown to result from intrinsic defects/traps in MoS2. At higher temperatures a second, independent mechanism of charge trapping and de-trapping between the oxide and p+ Si gate leads to hysteresis collapse at ~350 K and anti-clockwise hysteresis (inversion) for temperatures >350 K. The intrinsic-oxide trap model has been corroborated through device simulations. Further, pulsed current–voltage (I–V) measurements were carried out to extract the trap time constants at different temperatures. Non-volatile memory and temperature sensor applications exploiting temperature dependent hysteresis inversion and its reversibility in MoS2 transistors have also been demonstrated.

Ir/Al multilayer Gates for High Temperature Operated AlGaN/GaN HEMTs

The fabrication and characterization of the sequentially evaporated Ir/Al multilayer gates of AlGaN/GaN circular high electron mobility transistors formed by high temperature oxidation is reported. Annealing at temperature of 800 °C, for 60 s in O2 ambient makes possible to form a sharp gate interface with a high Schottky barrier height at RT (φb = 1.2 eV). It is also shown that high temperature oxidation can be an effective approach in reducing of both the gate and drain leakage currents of high electron mobility transistors (more than six orders). A comprehensive microstructural, electrical, and electro‐thermal characterization of the Ir/Al gates is carried out to study the thermal stability of the gate interface and high temperature performance of the devices. Stable operation of the devices with multilayer Ir/Al gates in the temperature range up to 500 °C is demonstrated. Here, it is proposed that the thermal stability of the interface is controlled by the formed aluminum oxide interfacial layer. Finally, perfectly clear pinch‐off characteristics and thermally induced threshold voltage (Vth) instability as low as −0.58 mV °C−1 are achieved.

Inert gas annealing effect in solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors

In this paper, the annealing effect of solution-processed amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO TFTs), under ambient He (He-device), is systematically analyzed by comparison with those under ambient O2 (O2-device) and N2 (N2-device), respectively. The He-device shows high field-effect mobility and low subthreshold slope owing to the minimization of the ambient effect. The degradation of the O2- and N2-device performances originate from their respective deep acceptor-like and shallow donor-like characteristics, which can be verified by comparison with the He-device. However, the three devices show similar threshold voltage instability under prolonged positive bias stress due to the effect of excess oxygen. Therefore, annealing in ambient He is the most suitable method for the fabrication of reference TFTs to study the various effects of the ambient during the annealing process in solution-processed a-IGZO TFTs.

Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and −3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (∼0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device, while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (∼0.14 eV above EF) and trapping at the oxide/GaN cap interface states.