Annealing, temperature, and bias-induced threshold voltage instabilities in integrated E/D-mode InAlN/GaN MOS HEMTs

Abstract

Threshold voltage instabilities are examined in self-aligned E/D-mode n++ GaN/InAlN/GaN MOS HEMTs with a gate length of 2 μm and a source-drain spacing of 10 μm integrated in a logic invertor. The E-mode MOS HEMT technology is based on selective dry etching of the cap layer which is combined with Al2O3 grown by atomic-layer deposition at 380 K. In the D-mode MOS HEMT, the gate recessing is skipped. The nominal threshold voltage (VT) of E/D-mode MOS HEMTs was 0.6 and −3.4 V, respectively; the technology invariant maximal drain current was about 0.45 A/mm. Analysis after 580 K/15 min annealing step and at an elevated temperature up to 430 K reveals opposite device behavior depending on the HEMT operational mode. It was found that the annealing step decreases VT of the D-mode HEMT due to a reduced electron injection into the modified oxide. On the other hand, VT of the E-mode HEMT increases with reduced density of surface donors at the oxide/InAlN interface. Operation at the elevated temperature produces reversible changes: increase/decrease in the VT of the respective D-/E-mode HEMTs. Additional bias-induced experiments exhibit complex trapping phenomena in the devices: Coaction of shallow (∼0.1 eV below EC) traps in the GaN buffer and deep levels at the oxide/InAlN interface was identified for the E-mode device, while trapping in the D-mode HEMTs was found to be consistent with a thermo-ionic injection of electrons into bulk oxide traps (∼0.14 eV above EF) and trapping at the oxide/GaN cap interface states.