Threshold Voltage Instability Research Articles

The effects of electric field and gate bias pulse on the migration and stability of ionized oxygen vacancies in amorphous In–Ga–Zn–O thin film transistors

Oxygen vacancies have been considered as the origin of threshold voltage instability under negative bias illumination stress in amorphous oxide thin film transistors. Here we report the results of first-principles molecular dynamics simulations for the drift motion of oxygen vacancies. We show that oxygen vacancies, which are initially ionized by trapping photoexcited hole carriers, can easily migrate under an external electric field. Thus, accumulated hole traps near the channel/dielectric interface cause negative shift of the threshold voltage, supporting the oxygen vacancy model. In addition, we find that ionized oxygen vacancies easily recover their neutral defect configurations by capturing electrons when the Fermi level increases. Our results are in good agreement with the experimental observation that applying a positive gate bias pulse of short duration eliminates hole traps and thus leads to the recovery of device stability from persistent photoconductivity.

Compact model for parametric instability under arbitrary stress waveform

A deterministic compact model of the parametric instability of elementary devices is further developed. The model addresses the device instability class that can be traced back to microscopic reactions obeying reversible first-order kinetics. It can describe the response to any periodic stimulus waveform and it is suitable for the implementation in commercial electronic circuit simulators (Eldo UDRM). The methodology is applied to model the negative-bias-temperature threshold voltage instability of a p-channel MOSFET. A simple circuital example is shown where the simulation of threshold voltage recovery is crucial for circuit design.

Impact of the array background pattern on cycling-induced threshold-voltage instabilities in nanoscale NAND Flash memories

This paper highlights that cycling-induced threshold-voltage instabilities in nanoscale NAND Flash technologies display a non-negligible dependence on the background pattern of the memory array during idle/bake periods. Experimental results clearly reveal, in fact, that instabilities in a (victim) cell do not depend only on its memory state, but also on the memory state of its first neighboring (aggressor) cells. The magnitude of this new cell-to-cell interference effect, moreover, appears to depend on the memory state of the victim cell, decreasing with the increase of its threshold-voltage level. From all of the gathered experimental evidence a physical picture explaining the phenomenon is provided, which is, finally, confirmed with the help of numerical simulations.

P‐20: The Effect of Oxide‐TFT Design on Voltage‐Threshold Shift

The threshold voltage (Vth) instability of oxide TFT is the largest hindrance to mass production. Stability improvement mainly focuses on the material and the process adjustment. Results in this study show that reasonable designs (such as floating SD, IGZO separation, etc.)reduce Vth shift. The influence mechanism of TFT shape to Vth shift is discussed in this paper.

Transparent Semiconducting Oxide Technology for Touch Free Interactive Flexible Displays

Amorphous oxide semiconductor thin film transistors and sensors constitute fundamental building blocks for a new generation of applications ranging from interactive displays and imaging to future electronic systems that are unconstrained by form factor. This makes the quest for high mobility materials processed at low temperatures even more compelling, to enable the layering of circuits and systems on plastic and possibly even paper substrates. Transparency is also an attractive feature that enables seamless embedding of electronics for the immersive ambient. This paper reviews the current status of the ubiquitous oxide semiconductor technology for flexible and transparent interactive displays, along with demonstrated examples of continuous thin film and nanowire systems for the transistor and sensor. Issues related to photo-sensing and active matrix operation are discussed along with solutions addressing the problem of threshold voltage instability and its compensation for fast recovery, particularly after light stress. Physics-based compact models for expedient design and simulation of analog and digital circuits are reviewed along with examples of key system building blocks. Finally we attempt to conceptualize a thin film transistor (TFT)-based fully heterogeneously integrated and autonomous system that can be realized using a combination of oxide and other technological routes.

Threshold Voltage Instability in 4H-SiC MOSFETs With Phosphorus-Doped and Nitrided Gate Oxides

Threshold voltage instability was investigated for 4H-SiC MOSFETs with phosphorus-doped (POCl3-annealed) and nitrided (NO-annealed) gate oxides. Threshold voltage shift observed in the bidirectional drain current–gate voltage characteristics was evaluated using various gate voltage sweeps at room and elevated temperatures up to 200 °C. The threshold voltage shift was also studied after applying positive and negative bias-temperature stress. Two types of MOSFETs showed different instability characteristics, depending on gate biases and temperatures. These features were found to originate from the difference in trap density and trap location at/near the oxide/SiC interface and in the oxide. It is apparent that the oxide traps in phosphorus-doped oxides and near-interface traps in nitrided oxides are the main origin of the threshold voltage instability via capture and emission (in the case of oxide traps, only capture) of both electrons and holes.

Basic Mechanisms of Threshold-Voltage Instability and Implications for Reliability Testing of SiC MOSFETs

A review of the basic mechanisms affecting the stability of the threshold voltage in response to a bias-temperature stress is presented in terms of the charging and activation of near-interfacial oxide traps. An activation energy of approximately 1.1 eV was calculated based on new experimental results. Implications of these factors, including the recovery of some bias-temperature stress-activated defects, for improved device reliability testing are discussed.

A Light-induced Threshold Voltage Instability Based on a Negative-U Center in a-IGZO TFTs with Different Oxygen Flow Rates

A Light-induced Threshold Voltage Instability Based on a Negative-U Center in a-IGZO TFTs with Different Oxygen Flow Rates

Microwave annealing effect for highly reliable biosensor: dual-gate ion-sensitive field-effect transistor using amorphous InGaZnO thin-film transistor.

We used a microwave annealing process to fabricate a highly reliable biosensor using amorphous-InGaZnO (a-IGZO) thin-film transistors (TFTs), which usually experience threshold voltage instability. Compared with furnace-annealed a-IGZO TFTs, the microwave-annealed devices showed superior threshold voltage stability and performance, including a high field-effect mobility of 9.51 cm(2)/V·s, a low threshold voltage of 0.99 V, a good subthreshold slope of 135 mV/dec, and an outstanding on/off current ratio of 1.18 × 10(8). In conclusion, by using the microwave-annealed a-IGZO TFT as the transducer in an extended-gate ion-sensitive field-effect transistor biosensor, we developed a high-performance biosensor with excellent sensing properties in terms of pH sensitivity, reliability, and chemical stability.

Design of step composition gradient thin film transistor channel layers grown by atomic layer deposition

In this study, we proposed the artificially designed channel structure in oxide thin-film transistors (TFTs) called a “step-composition gradient channel.” We demonstrated Al step-composition gradient Al-Zn-O (AZO) channel structures consisting of three AZO layers with different Al contents. The effects of stacking sequence in the step-composition gradient channel on performance and electrical stability of bottom-gate TFT devices were investigated with two channels of inverse stacking order (ascending/descending step-composition). The TFT with ascending step-composition channel structure (5 → 10 → 14 at. % Al composition) showed relatively negative threshold voltage (−3.7 V) and good instability characteristics with a reduced threshold voltage shift (Δ 1.4 V), which was related to the alignment of the conduction band off-set within the channel layer depending on the Al contents. Finally, the reduced Al composition in the initial layer of ascending step-composition channel resulted in the best field effect mobility of 4.5 cm2/V s. We presented a unique active layer of the “step-composition gradient channel” in the oxide TFTs and explained the mechanism of adequate channel design.

Mechanisms of thermally induced threshold voltage instability in GaN-based heterojunction transistors

In this work, we attempt to reveal the underlying mechanisms of divergent VTH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows “deeper” interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices.

Structure, bonding, and passivation of single carbon-related oxide hole traps near 4H-SiC/SiO2 interfaces

Single carbon interstitial in silicon dioxide, existing in carboxyl configuration, is shown to act as a border hole trap near 4H-SiC/SiO2 interface. Using density functional theory-based formation energy considerations, it is found to switch charge state between +2 and neutral as the 4H-SiC Fermi level sweeps its charge transition level located 1.4 eV above 4H-SiC valence band edge. Thus, carboxyl defect is predicted to be a potential candidate for threshold voltage instability in 4H-SiC MOSFETs. Post oxidation annealing of the interface with nitric oxide is shown to remove carboxyl defects. However, treating the defect in H2 creates a hole trap level at 1.1 eV above 4H-SiC valence band edge similar to the original carboxyl defect. The stability of carboxyl and H2 treated carboxyl defects in their doubly positive state is explained on the basis of their structural and bonding transformations during hole capture. These include puckering and back-bonding of silicon with lattice oxygen as in the well-known oxygen vacancy (E′ center) hole traps and an increase in the bond order between carboxyl carbon and oxygen.

Fowler-Nordheim tunneling at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors

The conduction mechanisms and trapping effects at SiO2/4H-SiC interfaces in metal-oxide-semiconductor field effect transistors (MOSFETs) were studied by Fowler-Nordheim (FN) tunnelling and frequency dependent conductance measurements. In particular, the analysis of both MOS capacitors and MOSFETs fabricated on the same wafer revealed an anomalous FN behavior on p-type implanted SiC/SiO2 interfaces. The observed FN instability upon subsequent voltage sweeps was correlated to the charge-discharge of hole trap states close the valence band edge of 4H-SiC. The charge-discharge of these traps also explained the recoverable threshold voltage instability observed in lateral MOSFETs.

Investigation on the Impact of Program/Erase Cycling Frequency on Data Retention of Nanoscale Charge Trap Nonvolatile Memory

This letter presents a detailed study to investigate the impact of program/erase (P/E) cycling frequency on threshold voltage (Vt) instability of nanoscale nitride-based charge trap nonvolatile memory (NB-CTNVM) devices. Post-P/E cycled Vt instability was found to exacerbate with higher P/E cycling frequency, which resulted in lower activation energy (Ea). The Ea obtained is 30% higher than those of floating gate NVM. In view of future demand for faster write speed of NVM devices, these findings indeed have critical impact on the selection of the acceleration factor and Ea applied to assess accurately the reliability performance of nanoscale CTNVM.

Accelerated degradation data of SiC MOSFETs for lifetime and Remaining Useful Life assessment

The phenomenon of threshold voltage instability has been reported to be a critical issue for the first generation of commercial SiC MOSFETs. For aeronautic mission profile, the long term reliability of such device has to be estimated prior to any integration. As far as the author knows, this paper proposes one of the first attempts to use a non-homogeneous gamma process to model the threshold voltage degradation of a commercial SiC MOSFET. Such approach allows evaluating the time to failure as well as it distribution thanks to the proposed Acceleration degradation testing methodology. All the data collected during the ageing tests will be used to model an acceleration factor and to extrapolate the Time-To-Failure in a given application. Ultimately, the use of gamma process to evaluate the Remaining Useful Life of electronic component is described as a first step toward prognostic of Remaining Useful Life in embedded power electronics.

Reliability of Commercially Available SiC Power Mosfets

With the introduction of SiC power MOSFETs into the commercial market place, it is critically important to determine the reliability of these devices. A number of potential issues need to be addressed, including the stability of the device threshold voltage, and the reliability of both the body diode and the gate oxide. An ideal switch has minimal leakage current in the OFF state and very low resistance in the ON state. But an excess negative shift of the threshold voltage under high-temperature reverse-bias (HTRB) conditions can lead to a critical increase in OFF-state leakage current and potential device failure [1]. In a similar fashion, a large positive shift of the threshold voltage may occur under high-temperature gate-bias (HTGB) conditions, wherein a positive bias-temperature stress is applied. This can lead to a significant increase in the ON-state resistance.This work focuses on the stability of the device threshold voltage when subject to bias-temperature stressing, although the reliability of the body diode will also be discussed in the full paper. The primary defects that contribute to shifts in the threshold voltage are near-interfacial oxide traps [2, 3]. A certain number of defect states become activated during device processing. This can vary depending on the details of the processing steps, or may be a function of device design. Typical instabilities of the threshold voltage at room temperature are about 0.25 V. Much larger threshold-voltage instabilities are observed following bias-temperature gate-bias stressing. This is very likely due to the activation of additional oxide traps, which can then participate in the oxide-trap charging process [3]. Since this activation is a function of time at temperature (and bias), more stressful processing conditions can quicken the onset of significant shifts in the threshold voltage during bias-temperature stressing. (Similarly, stressing at higher temperatures also leads to an earlier onset of significant increases in threshold-voltage instability.)As a result, we have observed a marked difference in the onset of significant increases in threshold-voltage instability between different commercial vendors. This difference in bias-temperature stress time can vary in some cases by two orders of magnitude. Detailed results will be provided in the full paper.

Characterization of Reliability in SiC Power Devices

The low intrinsic carrier concentrations, high breakdown voltages, and high thermal conductivities of wide-bandgap semiconductors make them attractive alternatives to traditional Si-based power electronics, especially for high-temperature/power switching applications such as motor drives, hybrid electric vehicles, and photovoltaic inverters. Silicon Carbide (SiC) is an especially strong candidate to replace Si devices due to widespread availability of SiC substrates, vertical device topologies, and the ability to thermally grow a silicon dioxide (SiO2) layer on SiC to serve as a gate dielectric, similar to established Si technology.SiC MOSFETs have been commercially available for over three years with blocking voltage of 1200V and excellent on-state resistances (~80 mΩ). In addition, SiC MOSFETs may be able to operate at higher temperatures than competing Si IGBTs or MOSFETs. Currently the most significant hurdles to market penetration are reliability and cost.SiC MOSFET reliability challenges stem mainly from poor SiC/SiO2 interface quality. When operated under high gate field and temperatures, threshold voltage (VT) instabilities are often observed both in SiC MOSFET [1] and MOS capacitor [2] structures, primarily due to the large number of electrically active SiO2 bulk and SiC/SiO2 interface states [3].The application of a gate voltage (VG) may result in electron (positive VG) or hole (negative VG) injection from the SiC into the oxide, populating traps at the SiO2/SiC interface and/or within the SiO2 bulk. These populated traps alter the surface potential and shift the VT necessary to switch the device. Recent measurements on second-generation commercially available SiC MOSFETs indicate significant progress on this front compared to earlier devices, although appreciable VTshifts still exist for relatively moderate stresses (Fig. 1a).We have characterized 1200 V SiC MOSFETs as well as Junction FETs (JFETs), which do not utilize a gate oxide, at high temperatures under both static and dynamic gate bias stress conditions. SiC JFET devices demonstrate more stable VT than SiC MOSFET devices for both types of gate bias stresses at high temperatures (Fig. 1b). For static gate bias stresses, packaged JFET devices exhibited a negligible VT shift (ΔVT < 2 mV) for temperatures up to 250oC. At higher temperatures, bare JFET die demonstrated ΔVT < 10 mV up to 525oC. Further, in contrast to the SiC MOSFETs, the VTof the SiC JFETs was unaffected by dynamic gate bias stress over the test period, although the sub-threshold leakage current increased with time [4].In addition to monitoring VT shifts, we have calculated the change in density of SiC/SiO2 interface traps (ΔDIT) due to the application of gate stress to MOSFETs. These profiles can be extracted from I-V curves for SiC MOSFETs based on the changes in sub-threshold slope. This technique can either be used to determine ΔDIT (if body doping and gate capacitance are unknown) or absolute DIT at specific energies within the bandgap (if doping and capacitance are known) [5].This work was performed under the DOE Office of Electricity programs managed by Dr. Imre Gyuk. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000.[1] A. J. Lelis, et al., "Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements," IEEE Trans. Electr. Dev., vol. 55 (8), pp. 1835-1840, 2008.[2] M. J. Marinella, et al., "Evidence of Negative Bias Temperature Instability in 4H-SiC Metal Oxide Semiconductor Capacitors," Appl. Phys. Lett., vol. 90 (25), pp. 253508-253508, 2007.[3] D. K. Schroder, "Progress In SiC Materials/Devices and Their Competition," Int. J. High Speed Electr. and Syst., vol. 21 (1), p. 1250009, Apr 2012.[4] J. Flicker, et al., "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs and JFETs at High Temperatures," High Temperature Electronics Conference (HiTEC), Albuquerque, NM, 2014.[5] D. R. Hughart, et al., "Sensitivity Analysis of a New Technique for Trapped Charge Extraction in SiC MOSFETs from Subthreshold Characteristics " International Reliability Physics Symposium (IRPS), Waikoloa, HI, 2014.

Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part II: On-Field Operation and Distributed-Cycling Effects

Starting from the theoretical background on the detrapping process in nanoscale Flash memories given in Part I of this paper [1], we address here the effect of idle periods, temperature, and program/erase cycles on the spectral distribution of detrapping events and, in turn, on threshold-voltage instabilities appearing during a data retention time stretch. In so doing, we come to a comprehensive model able to deal with threshold-voltage instabilities from whatever on-field usage or testing scheme of the memory array, carefully accounting for both charge trapping and detrapping, and reproducing distributed-cycling effects. The model represents a valuable tool for the predictive reliability analysis of Flash technologies and for the development of accelerated experimental schemes for the assessment of post-cycling thereshold-voltage instabilities coming from charge detrapping.

Revisiting Charge Trapping/Detrapping in Flash Memories From a Discrete and Statistical Standpoint—Part I: \(V_{T}\) Instabilities

This paper and the corresponding Part II [1] revisit charge trapping and detrapping in Flash memories considering some major features of the phenomenon which have been clearly detected on nanoscale technologies: charge discreteness, statistical charge capture and emission, statistical distribution of the threshold-voltage shift following a charge capture/emission event, and spectral distribution of the detrapping time constants over many decades of time. In this Part I, we address threshold-voltage instabilities following charge detrapping from the cell tunnel oxide, highlighting their statistical properties and coming to a powerful formula for their quantitative analysis. These results pave the way to the development of a comprehensive statistical model able to deal with charge trapping/detrapping during whatever on-field array operation, representing the topic of Part II.

In situ x-ray photoelectron spectroscopy and capacitance voltage characterization of plasma treatments for Al2O3/AlGaN/GaN stacks

We investigate the Al2O3/AlGaN/GaN metal-oxide-semiconductor structure pretreated by O2 anneals, N2 remote plasma, and forming gas remote plasma prior to atomic layer deposition of Al2O3 using in situ X-ray photoelectron spectroscopy, low energy electron diffraction, and capacitance- voltage measurements. Plasma pretreatments reduce the Ga-oxide/oxynitride formation and the interface state density, while inducing a threshold voltage instability.