Threshold Voltage Instability Research Articles

Non-homogenous gamma process: Application to SiC MOSFET threshold voltage instability

The accelerated degradation tests provide the opportunity to assess the reliability of an electronic component for which only parametric degradation is observable. In the case of the silicon carbide MOSFETs, this approach makes it possible to study the impact of the threshold voltage phenomenon on the reliability of the devices. During the High Temperature Gate Bias tests, we have carried out, the threshold voltage of the ten devices under test have been monitored and their degradation modeled using a non-homogeneous Gamma process. The estimation of the degradation process parameters enable to estimate the distribution of the first hitting time to a degradation threshold which is considered as a failure criterion. Lastly, a criterion proposed by Tseng and Yu [1] has been used to provide a metric to stop these ageing tests while having relevant reliability data.

Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET

The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10-6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.

High-performance normally off AlGaN/GaN-on-Si HEMTs with partially recessed SiN x MIS structure

Recessed MIS gate structures with SiNx gate dielectric layer were investigated for use in normally off AlGaN/GaN-on-Si high electron mobility transistors (HEMTs). The channel mobility and threshold voltage (Vth) instability were strongly affected by the recessed configuration. Employing a 30 nm SiNx gate dielectric layer composed of 6 nm PEALD and 24 nm ICP-CVD films on a 2 nm AlGaN recessed barrier layer resulted in excellent electrical and dynamic characteristics with reduced effective interface trap density. A maximum drain current density of 590 mA mm−1, an on-resistance of 0.75 mΩ · cm2, and a breakdown voltage of >1100 V were achieved for the gate-to-drain distance of 10 μm. Owing to the remaining AlGaN barrier layer under the recessed gate region of the partially recessed device, the interaction between MIS interface traps and channel electrons was suppressed effectively, resulting in improved channel mobility and Vth stability.

The Effect of Charge Redistribution on Flat-Band Voltage Turnaround in 4H-SiC MOS Capacitors

The existence of a turnaround in flat-band voltage shift of stressed MOS capacitors, fabricated on N-type 4H–SiC substrates, is reported in this paper. The turnaround is observed by room-temperature C–V measurements, after two minutes gate-bias stressing of the MOS capacitors at different temperatures. The existence of this turnaround effect demonstrates that a mechanism, in addition to the well-stablished tunneling to the near-interface oxide traps, is involved in the threshold voltage instability of 4H–SiC MOSFETs. This newly identified mechanism occurs due to charge redistribution of the compound polar species that exist in the SiO2–SiC transitional layer.

Experimental evidences of charge transition levels in ZrO2 and at the Si: ZrO2 interface by deep level transient spectroscopy

The native defects in zirconium oxide (ZrO2) and defects at the ZrO2/Si interface lead to threshold voltage shifts, Fermi level pinning, and various other reliability concerns. It is necessary to recognize the origin of these defects and to quantify them. A large number of theoretical reports deal with oxygen vacancy related defect states in the ZrO2 films; however, the large band gap limits the experimental assessments. In this study, we have deployed Deep Level Transient Spectroscopy to study the deep level defects present in high-κ ZrO2 gate dielectrics and at the Si:ZrO2 interface. The band alignment of the Al/ZrO2/Si stack was derived from Ultraviolet Photo electron Spectroscopy measurement to find the exact locations of trap levels. Five deep levels were observed in the band gap of ZrO2; these are related to different charge states of oxygen vacancies. The activation energies of these trap states are in the range of 1.16–1.84 eV from the ZrO2 conduction band. The capture cross-section of these states was also measured and found to be quite low (10−21 cm2). The small value of capture cross-sections is attributed to tunneling events occurring between the energy levels of the bulk and interface. This study would aid in the understanding of numerous fascinating facts witnessed in ZrO2, such as resistive switching, threshold voltage instabilities, and leakage current problems associated with oxygen vacancy related traps.

Role of Oxygen Vacancies in Short- and Long-Term Instability of Negative Bias-Temperature Stressed SiC MOSFETs

We use hybrid-functional density functional theory to study the role of oxygen vacancies in negative bias-and-temperature stress-induced threshold voltage instability in 4H-silicon carbide power MOSFETs. According to our model, certain originally electrically “inactive” oxygen vacancies are structurally transformed into electrically “active” defects in the presence of strong negative bias and temperature. These newly generated defect configurations function as short-lived or long-lived switching oxide hole traps. The transients of their generation process are shown to correlate well with the measured “short-term” threshold voltage instability. Additionally, we show that the long-lived defects continue to degrade the room-temperature reliability of these devices even after stress removal.

Characterization of Interface Defects With Distributed Activation Energies in GaN-Based MIS-HEMTs

Charge trapping is one of the main reliability issues for GaN-based MIS-high-electron-mobility-transistor technologies. In this paper, we focus on the defects located at or close to the interface with the dielectric, which are responsible for the threshold voltage instability at positive gate bias conditions. We present a methodology to analyze the experimental data based on the nonradiative multiphonon model for charge trapping. In particular, we show how to extract the density of interface traps as a function of their activation energy from stress and recovery experiments performed at various temperatures. Our approach is applied to two GaN/AlGaN/SiN samples with different trapping properties, at temperatures ranging from −190 °C to 200 °C. We evaluate their response to forward bias stress and finally, we extract the activation energy distribution for electron capture and emission over a continuous energy range.

High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (∼17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (∼87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH−1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part I: Experimental Evidence

By using our 16-nm NAND Flash technology as a test vehicle, in this paper, we summarize all the experimental evidence that we have gathered so far on the phenomenology of cycling-induced charge trapping/detrapping in Flash memories. In particular, results from experiments conceived to explore the dependence of charge detrapping on cell memory state reveal that the phenomenon involves more than the simple capture and emission of charge carriers in tunnel-oxide defects. Besides, the thermal activation of charge trapping is highlighted for the first time, along with the detailed dynamics leading to the increase of the trapped charge as cell cycling proceeds. These results allow to lay some cornerstones for the microscopic description of cyclinginduced charge trapping/detrapping in Flash memories. From these cornerstones, in the companion paper (Resnati et al. , 2016), a new physical picture for the trapping/detrapping processes will be proposed and implemented in a statistical model able to reproduce their corresponding threshold-voltage instabilities over array lifetime.

Cycling-Induced Charge Trapping/Detrapping in Flash Memories—Part II: Modeling

Starting from all the experimental evidence we presented in Part I of this work (Resnati et al., 2016), in this paper, we propose a new microscopic picture for cycling-induced charge trapping/detrapping in Flash memories. This picture involves structural relaxation of the charged tunnel-oxide defects as limiting step in the detrapping process, triggering the possibility for defects to exchange carriers with the substrate. This view is implemented in a statistical model able to reproduce the threshold-voltage instability coming from the phenomenon, including its dependence on cycling dose, temperature, and cell state during idle/bake periods. The model is then used to address some elaborated accelerated testing schemes commonly used to monitor charge trapping/detrapping and its related instability in Flash memories, explaining their results in the context of the new proposed picture of the phenomenon.

Effects of interface states and near interface traps on the threshold voltage stability of GaN and SiC transistors employing SiO2 as gate dielectric

This paper reports on the effects of interface states and near interface traps on the behavior of GaN and SiC transistors employing SiO2 as gate dielectric, emphasizing the role of these interfacial charged traps on the threshold voltage stability of the devices. Capacitance, conductance, and current measurements, carried out as a function of the frequency, were used to characterize the GaN- and SiC-metal-oxide-semiconductor systems. In these systems, although postoxide deposition annealing treatments reduce the interface states density, the presence of near interface traps can induce an anomalous behavior of the current conduction, accompanied by a threshold voltage instability. The transfer characteristics of the transistors acquired in an appropriate bias range enabled to quantify the density of these traps in the order of 1011 cm−2.

Subgap States near the Conduction-Band Edge Due to Undercoordinated Cations in Amorphous In-Ga-Zn-O and Zn-Sn-O Semiconductors

Amorphous oxide semiconductors are promising channel materials for transparent, flexible thin-film transistors, but actual devices suffer from instability in threshold voltage, due to structural defects. First-principles calculations reveal that undercoordinated cations in nonstoichiometric samples lead to localized subgap states that are the root of the instability. These results establish a physical understanding of the precise origin of these states, and offer guidance to control such defects for successful applications.

Improving the radiation hardness of graphene field effect transistors

Ionizing radiation poses a significant challenge to the operation and reliability of conventional silicon-based devices. Here, we report the effects of gamma radiation on graphene field-effect transistors (GFETs), along with a method to mitigate those effects by developing a radiation-hardened version of our back-gated GFETs. We demonstrate that activated atmospheric oxygen from the gamma ray interaction with air damages the semiconductor device, and damage to the substrate contributes additional threshold voltage instability. Our radiation-hardened devices, which have protection against these two effects, exhibit minimal performance degradation, improved stability, and significantly reduced hysteresis after prolonged gamma radiation exposure. We believe this work provides an insight into graphene's interactions with ionizing radiation that could enable future graphene-based electronic devices to be used for space, military, and other radiation-sensitive applications.

Trap behaviours characterization of AlGaN/GaN high electron mobility transistors by room-temperature transient capacitance measurement

In this paper, the trap behaviours in AlGaN/GaN high electron mobility transistors (HEMTs) are investigated using transient capacitance measurement. By measuring the transient gate capacitance variance (ΔC) with different pulse height, the gate pulse induced trap behaviours in SiNX gate dielectric layer or at the SiNX/AlGaN interface is revealed. Based on the results, a model on electron traps in AlGaN/GaN HEMTs is proposed. The threshold voltage (Vth) instability in AlGaN/GaN HEMTs is believed to be correlated with the presence of these traps in SiNX gate dielectric layer or at the SiNX/AlGaN interface. Furthermore, trap density before and after step-stress applied on drain electrode is quantitatively analyzed based on ΔC measurement.

Intrinsic Robustness of TFET Subthreshold Swing to Interface and Oxide Traps: A Comparative PBTI Study of InGaAs TFETs and MOSFETs

We study the positive bias temperature instability (PBTI) of InGaAs tunnel-FETs (TFETs) with two different indium fractions (53% and 70%) and compare with reference MOSFETs, using the same gate stack. While identical threshold voltage instability is found irrespective of the device type, the subthreshold swing (SS) of the TFETs is found to be more robust against PBTI as compared with MOSFETs. With the aid of comprehensive TCAD simulations, we show that the SS of a TFET is intrinsically less sensitive to interface/oxide border traps, thanks to the narrow energy range swept by the channel Fermi level during the OFF-to-ON transition of the device operation. Moreover, only traps located within ~20 nm from the tunnel junction can affect the SS.

Device physics towards high performance GaN-based power electronics

Gallium-nitride-based power electronic devices, with the inherent high breakdown voltage, high working frequency, high output current density and high temperature operating capability, are promising candidates for next-generation high-efficiency and compact power management systems. In this work, the scientific and technical challenges towards high-performance GaN power devices, including threshold voltage instability, dynamic ON-resistance degradation, enhancement-mode gate techniques and long-term reliability of gate dielectrics, are investigated based on in-depth analysis of the physical origin of interface states and high-voltage current collapse. Oxidation of (Al) GaN surface are suggested to be the primary cause for the surface/interface states in GaN-based power devices. State-of-the-art device technologies, including nitridation-interficial-layer to suppress dielectric/(Al) GaN interface oxidation, polarized PEALD-AlN passivation for compensation of deep interface states, E-mode techniques of fluorine plasma ion implantation and high-temperature low-damage gate-recess, high-breakdown-strength LPCVD-SiN x and O3-sourced ALD-Al2O3 gate dielectrics are introduced for fabrication of high performance and reliability GaN-based power electronic devices.

Effect of hydrogen on dynamic charge transport in amorphous oxide thin film transistors

Hydrogen in zinc oxide based semiconductors functions as a donor or a defect de-activator depending on its concentration, greatly affecting the device characteristics of oxide thin-film transistors (TFTs). Thus, controlling the hydrogen concentration in oxide semiconductors is very important for achieving high mobility and minimizing device instability. In this study, we investigated the charge transport dynamics of the amorphous semiconductor InGaZnO at various hydrogen concentrations as a function of the deposition temperature of the gate insulator. To examine the nature of dynamic charge trapping, we employed short-pulse current−voltage and transient current−time measurements. Among various examined oxide devices, that with a high hydrogen concentration exhibits the best performance characteristics, such as high saturation mobility (10.9 cm2 v−1 s−1), low subthreshold slope (0.12 V/dec), and negligible hysteresis, which stem from low defect densities and negligible transient charge trapping. Our finding indicates that hydrogen atoms effectively passivate the defects in subgap states of the bulk semiconductor, minimizing the mobility degradation and threshold voltage instability. This study indicates that hydrogen plays a useful role in TFTs by improving the device performance and stability.

Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

Impact of Al Doping Concentration at Channel Region on Mobility and Threshold Voltage Instability in 4H-SiC Trench N-MOSFETs

The effect of Al doping concentration (NA) at channel regions ranging from 1.0×1017 to 4.0×1017 cm-3 on the effective channel mobility of electron (μeff) and the threshold voltage (Vth) instability under the positive bias-temperature-stress conditions has been investigated througu the use of trench-gate 4H-SiC MOSFETs with m-face (1-100) channel regions. It was found that μeff degraded with an increase in NA. On the other hand, the increase of NA enlarged the Vth instability. These results indicate that NA has a large impact not only on the Vth value but also on the channel resistance and reliability in 4H-SiC trench MOSFETs.

On the Origin of Threshold Voltage Instability under Operating Conditions of 4H-SiC n-Channel MOSFETs

We report on the threshold voltage () instability under operating conditions after gate bias switches at constant drain voltage for n-MOSFETs fabricated on 4H silicon carbide (4H-SiC). This effect occurs at room temperature and close to the of the device. We show that the origin of the instability is electron trapping into SiO2 over an energy barrier of (0.3-0.4) eV. These traps show similarities to traps previously observed in 4H-SiC MOS capacitors and labelled near interface traps (NITs). Further, the density of the traps can be reduced by one order of magnitude through post-oxidation annealing in nitric oxide atmosphere.