Threshold Voltage Instability Research Articles

Effect of SiC Power DMOSFET Threshold-Voltage Instability

ABSTRACTWe have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs

In this work, the instability of n-channel 4H–SiC double-implanted metal–oxide–semiconductor field-effect-transistors (DMOSFETs) was studied, in terms of threshold-voltage ( V TH) shifts and drain–source current ( I DS) transients, for different gate bias stress durations of range 100–5500 s. At room temperature, for positive gate bias stress, the V TH shift and I DS decay increase with increasing stress time. The V TH shift and the I DS decay were recovered by negative gate bias stress. It is believed that the instability in device behavior during positive gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. Elevated temperature measurements have indicated a decrease in V TH and an increase in I DS with increasing stress time possibly due to mobile positive ions in the gate dielectric.

Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses

This paper reports the effects of high electric field stress (HEFS) and positive bias temperature instability (PBTI) in threshold voltage, input and Miller capacitances of N −channel power VDMOSFETs. The procedure used for this study is based on the analysis of the gate charge characteristics, the two-dimensional simulation of the structure, and the physical properties of the device. The gate charge characteristics investigated during and up to 500 h of HEFS and PBTI show some degradation of physical device properties. The results are analysed and parameters responsible of these degradations are extracted. It is shown that the main degradation issues in the Si power VDMOSFETs are the charge trapping and the trap creation at the interface of the gate dielectric, induced by energetic free carriers which have sufficient energy to cross the SiO 2/Si barrier.

Improvement on performance and reliability of TaN/HfO 2 LTPS-TFTs with fluorine implantation

In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO 2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I on/ I min current ratio 1.9 × 10 6 are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO 2/polysilicon interface. Significant improvements on subthreshold swing and I min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage ∼1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I on/ I min current ratio 1.21 × 10 7, which is suitable for the application of system-on panel (SOP).

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (Vth) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the Vth shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer.

Instability of threshold voltage under constant bias stress in pentacene thin film transistors employing polyvinylphenol gate dielectric

The instability of threshold voltage and mobility of pentacene thin film transistors using a poly(4-vinylphenol) gate dielectric have been investigated under constant bias stress. The mobility was very stable in vacuum by exhibiting 2% variation after 6 h stress even under the high gate bias stress of V GS = − 20 V. Meanwhile, we observe a negative shift of threshold voltage under stress in vacuum. This shift is attributed to charges trapped in deep electronic states in pentacene near the gate interface. We propose a model for the negative shift of the threshold voltage and extract the hole concentration, 4.5 × 10 11 cm − 2 , needed to avoid the onset of stress effects, resulting in a design rule of the channel width to length ratio larger than 40.

Instability of Threshold Voltage of Flexible Single-Crystal Si TFTs

N-type, top gate, single-crystal Si thin-film transistors (TFTs) using evaporated silicon monoxide (SiO) as the gate dielectric layer are fabricated on flexible plastic substrate. The threshold voltage (VT) instability of the device is studied by applying high gate voltages. VT shift to higher values under positive gate bias stress is observed. The logarithmic dependence of VT shift on time indicates that electrons are injected and trapped in the SiO layer from Si channel. The subthreshold swing degradation is also found after the stress, suggesting the generation of interface states at Si/SiO surface. However, under negative gate stress, VT firstly decreases and then increases after longer stress time. This is believed to be the combined effects of both holes injection from Si substrate and electrons emission from metal gate, for which the latter become dominant under a long- term stress.

Threshold voltage instability of p-channel metal-oxide-semiconductor field effect transistors with hafnium based dielectrics

Threshold voltage Vth instability is one major issue for future metal-oxide-semiconductor field effect transistors (MOSFETs) with hafnium (Hf) based gate dielectrics. Previous attention was focused on n-channel MOSFETs (nMOSFETs) and the implicit assumption is that it is not important for p-channel MOSFETs (pMOSFETs). This work shows that the Vth instability of pMOSEFTs can be higher than that of nMOSFETs for a sub-2nm nitrided Hf layer. Unlike nMOSFETs, the Vth instability of pMOSFETs is insensitive to measurement time, does not saturate as stress voltage increases, and is not controlled by carrier fluency. Using Hf silicates is less effective in suppressing it. Some speculations are given on the defect and physical processes responsible for the instability.

Impact of nitrogen in HfON gate dielectric with metal gate on electrical characteristics, with particular attention to threshold voltage instability

The impact of nitrogen (N) in HfON gate dielectric on electrical characteristics, particularly on charge trapping induced threshold voltage (Vth) instability, has been investigated in n-channel metal-oxide-semiconductor field effect transistor with TaN metal gate. Compared to HfO2, the enhanced gate capacitance, slightly increased gate leakage current, and degraded interface properties were observed in the HfON gate dielectric. The incorporation of N into HfO2 also caused mobility degradation at low effective field region. Moreover, charge trapping induced Vth instability was found to be severer in HfON than in HfO2, which could be attributed to increased bulk traps induced by the incorporated N.

Layout Dependence on Threshold Voltage Instability of Hydrogenated Amorphous Silicon Thin Film Transistors

In this paper, we discuss the threshold voltage instability of two distinct layouts of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs). By simultaneously applying gate and drain bias stress, we show that the average threshold voltage shift of circular a-Si:H TFTs is 54% less than that of conventional inverted staggered a-Si:H TFTs. This result is primarily due to that the circular layout reduces the channel electron concentration. ISE-DESSIS (Integrated System Engineering DEvice Simulation for Smart Integrated Systems) was used to simulate the parallel electric field and obtain the total channel electron concentration. The simulation results closely correspond to the explanation in this study. These results indicate a significant impact of improving threshold voltage stability by a layout method.

Mechanism of Electron Trapping and Characteristics of Traps in $\hbox{HfO}_{2}$ Gate Stacks

Electron trapping in high- gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes low-temperature threshold voltage instability in NMOS transistors with /TiN gate stacks.

Defects and their passivation in high K gate oxides

High dielectric constant oxides such as HfO 2 are very important as gate dielectrics in future CMOS devices. However, compared to SiO 2 they suffer from much higher defect concentrations which cause charge trapping, threshold voltage instability, and mobility degradation. The main defect is the oxygen vacancy. It has been found that fluorine is able to passivate these defects to an extent. The mechanism of defect passivation is calculated using ab-initio methods, and the general principles of defect passivation in ionic oxides are discussed.

Defect Passivation With Fluorine and Interface Engineering for Hf-Based High- <formula formulatype="inline"><tex>$k$</tex></formula>/Metal Gate Stack Device Reliability and Performance Enhancement

Using a fluorinated high-fc/metal gate stack combined with a stress relieved preoxide (SRPO) pretreatment before high-fc deposition, we show significant device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem, and performance degradation for high-fc is a concern. The novel fluorinated Ta <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> /HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /SRPO gate stack device exceeds the positive-bias-temperature-instability and negative-bias-temperature-instability targets with sufficient margin and has electron mobility at 1 MV/cm comparable to the industrial high-quality polySi/SiON device on bulk silicon.

Amorphous Silicon Display Backplanes on Plastic Substrates

Amorphous silicon (a-Si) thin-film transistor (TFT) backplanes are very promising for active-matrix organic light-emitting diode displays (AMOLEDs) on plastic. The technology benefits from a large manufacturing base, simple fabrication process, and low production cost. The concern lies in the instability of the TFTs threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and its low device mobility. Although V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -instability can be compensated by means of advanced multi-transistor pixel circuits, the lifetime of the display is still dependent on the TFT process quality and bias conditions. A-Si TFTs with field-effect mobility of 1.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots and pixel driver circuits have been fabricated on plastic substrates at 150 degC. The circuits are characterized in terms of current drive capability and long-term stability of operation. The results demonstrate sufficient and stable current delivery and the ability of the backplane on plastic to meet AMOLED requirements

Threshold Voltage Instability and Low Frequency Noise in Hafnium-Based Gate Dielectrics

This paper focus on two of the main reliability problems observed in Hafnium-based gate dielectrics: threshold voltage instability and low frequency noise. Both issues are ascribed to the Hf-Si bonds generated at the HfO2/polysilicon interface. These defects act as charge capture centers whose trapping probability decreases with the inverse of the number of injected charges. In the case of HfO2/polysilicon gate stack the drain low frequency noise increases of two orders of magnitude and the gate low frequency noise increases of three orders of magnitude with respect to SiO2/polysilicon gate stack. By using HfSiON as gate dielectrics or metal as gate electrode both reliability problems are strongly reduced.

Threshold-Voltage Instability of Single-Crystal Si Thin-Film Transistors Fabricated on Plastic Substrate

Single-crystal Si thin films are transferred onto plastic host substrate after selectively removing the buried oxide (BOX) layer on the silicon-on-insulator (SOI) substrate. A layer of SU-8 epoxy is used as gate dielectric for the thin-film transistors (TFTs) fabricated on the transferred Si thin films. Here we report the first observation of threshold voltage (Vt) instability on these n-type, single-crystal Si TFTs on flexible plastic substrate. It is observed that Vt shifts to higher (lower) value under high positive (negative) gate-bias stressing. The logarithmic time-dependence of the Vt shift suggests that the instability is attributed to charge trapping in the gate dielectric layer.

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).

An Assessment of the Location of As-Grown Electron Traps in$hboxHfO_2$/HfSiO Stacks

Replacing SiON by high-kappa layers is a pressing issue for CMOS technologies. The presence of as-grown electron traps in HfO2 is a major obstacle, since they can induce threshold-voltage instability, reduce electron mobility, and result in early breakdown. Their location has not been clarified and is addressed in this letter. By selecting test conditions carefully and using samples with a progressive reduction of HfO2 thickness, the authors are able to rule out that traps are piled up near the HfO2/HfSiO interface. A uniform distribution throughout HfO2 does not agree with the test data, either. Results support that trapping is negligible near to one or both ends of the HfO2 layer when compared with trapping in the central region

Charge Trapping & NBTI in High k Gate Dielectric Stacks

Over recent years, there has been increasing research and development efforts to replace SiO2 with high dielectric constant (k) materials such as HfO2, HfSiO, Al2O3. An important transistor reliability issue is the threshold voltage stability under prolonged stressing. In this paper, we discuss two main causes of threshold voltage instability: charge trapping and negative bias temperature instability (NBTI) in high k gate dielectric stacks. Experimental and modeling studies for these threshold voltage instabilities are reviewed.