Threshold Voltage Instability Research Articles

Positive Bias Temperature Instability Effects in nMOSFETs With $\hbox{HfO}_{2}/\hbox{TiN}$ Gate Stacks

The positive bias temperature instability (PBTI) and the stress-induced leakage current (SILC) effects are thoroughly examined in nFETs with SiO2/HfO2/TiN dual-layer gate stacks under a wide range of bias and temperature stress conditions. Experimental evidence of the SILC increase with time is obtained suggesting the activation of a trap generation mechanism. Threshold voltage (V T) instability is found to be the result of a complicated interplay of two separate mechanisms; filling of preexisting electron traps versus trap generation each one dominating at different stress condition regimes. Furthermore, V T instability relaxation experiments, undertaken at judiciously chosen conditions, show that the preexisting and stress-induced traps exhibit similar detrapping kinetics indicating that both types of traps may have similar characteristics. Finally, it is shown that the role of the SILC effect (and the associated trap generation component) on V T instability is process dependent and that SILC reduction is accompanied by enhancement of the PBTI device lifetime.

Impact of Sensing Gate Bias on NBTI of Hf-based Dielectric Stacks

The negative bias temperature instability (NBTI) is limiting the lifetime of pMOSFETs with SiON gate dielectric and it is generally believed that Hf-based dielectric stack has higher instability than SiON. As Hf-based dielectric stacks are replacing SiON, there is a pressing need for characterizing their NBTI. Traditionally, the threshold voltage instability, ΔVth, is evaluated with a sensing gate bias, Vgsense, close to Vth. Vth is lower than the digital circuit operation bias and the implicit assumption is that ΔVth is independent of Vgsense. This work will show that ΔVth for Hf-based stacks increases substantially when Vgsense rises from Vth to the operation level. This Vgsense effect should be taken into account when modeling the impact of NBTI on circuit operation in the future.

Performance and Stability Characterization of Bottom Gated Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Grown by RF and DC Sputtering

In this paper, the performance and the gate bias stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) with different channel sputtering conditions, RF and DC are studied. DC devices show excellent electrical characteristics but larger charge trapping and slower detrapping in relaxation period under the same gate bias stress. To understand the cause of stress behavior, traps are extracted by subthreshold slop and low-high frequency dependent capacitance measurement and compared before and after gate bias stress. The extracted trap densities well explain the process-dependent device properties like as threshold voltage, mobility and on/off current ratio, but are not dependent on bias stress. From current–voltage (I–V) and capacitance–voltage (C–V) measurement, we can conclude that the threshold voltage instability arises due to the process of temporary charge trapping which is dominant only at gate bias stress and the trapping/detrapping behavior is strongly dependent on the channel layer deposition condition.

Charge-transition levels of oxygen vacancy as the origin of device instability in HfO2 gate stacks through quasiparticle energy calculations

We perform quasiparticle energy calculations to study the charge-transition levels of oxygen vacancy (VO) in HfO2. The negative-U property of VO can explain flat band voltage shifts and threshold voltage (Vth) instability in hafnium based devices. In p+ Si gate electrode, the Fermi level pinning varies by up to 0.55 eV, in good agreement with the measured values. Depending on gate bias, VO traps electrons or holes from the Si channel, causing the Vth instability. It is suggested that short time-scale charge trapping/detrapping is due to metastable VO−1 centers, whereas stable VO−2 centers dominate long time-scale instability.

Implications of Threshold-Voltage Instability on SiC DMOSFET Operation

Although recent fast I-V measurements and subthreshold analysis reveal that the threshold-voltage instability due to low-field bias stressing at room temperature is greater than previously reported when calculated using slower, standard measurements by a parameter analyzer—a result that is consistent with electrons directly tunneling into and out of near interfacial oxide traps, this effect will not prevent the use of power SiC DMOSFET switches in power converter applications if certain precautions are followed. Namely, if the threshold voltage is set high enough so that a negative shift in threshold voltage will not increase the leakage current in the off-state, then the primary effect will be to increase the on-state resistance by decreasing the effective gate voltage. The instability due to ON-state stressing is greater than that for bias stressing alone, but not significantly. For a well behaved device, a 1-hour ON-state stress will result in about a 7 percent increase in conduction losses, which is manageable for power converter applications.

Drain bias dependent bias temperature stress instability in a-Si:H TFT

The threshold voltage ( V t) instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is investigated under drain bias dependent bias temperature stress ( V D-BTS). The drain bias reduces the overall gate overdrive stress and leads to a position-dependent V t-shift (Δ V t) with maximum Δ V t at the source-end and minimum Δ V t at the drain-side of channel. Measured Δ V t was compared with the calculated Δ V t using a weighted average of local V t-shift. The calculated Δ V t based on weighted average agreed better with the measured data in U-type samples, but a simple linear average over the channel agreed better with the measured data in an I-type sample. This is explained in terms of the fact that the source-side channel width is larger than the drain-side width in a U-type sample which results in more contribution from the source-side to the normalized Δ V t. A non-uniform V t profile due to V D-BTS resulted in a higher drain current in the forward measurement (source/drain are the same as in stress) than in reverse measurement (source/drain are interchanged from stress). This also leads to a different extracted V t in forward and reverse configurations due to the non-uniform V t profile along the channel. V t extracted from the saturation transfer curve varies significantly in different current ranges due to the gate bias dependence of field-effect mobility caused by a large variation of the overdrive voltage along the channel.

Spatial distribution of electrically active defects in dual-layer (SiO2∕HfO2) gate dielectric n-type metal oxide semiconductor field effect transistors

Spatial distributions of electrically active defects in dual-layer (SiO2∕HfO2) gate dielectric n-type metal oxide semiconductor transistors have been determined by charge pumping and 1∕f low-frequency noise measurements. Oxide trap concentration levels extracted from both techniques are in good agreement and appear one decade greater for HfO2 oxides compared to the reference SiO2 one. Moreover an increase in the trap concentration at the SiO2∕HfO2 is observed that could explain threshold voltage instabilities currently observed in HfO2 based transistors.

Temperature and Time Dependent Threshold Voltage Instability in 4H-SiC Power DMOSFET Devices

Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress time and inversely with temperature. This instability is explained with the trapping rate of channel electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the measured value of Vth approaches the theoretical value.

Origin of threshold voltage instability in indium-gallium-zinc oxide thin film transistors

We investigated the impact of the passivation layer on the stability of indium-gallium-zinc oxide (IGZO) thin film transistors. While the device without any passivation layer showed a huge threshold voltage (Vth) shift under positive gate voltage stress, the suitably passivated device did not exhibit any Vth shift. The charge trapping model, which has been believed to be a plausible mechanism, cannot by itself explain this behavior. Instead, the Vth instability was attributed to the interaction between the exposed IGZO backsurface and oxygen and/or water in the ambient atmosphere during the gate voltage stress.

Bias-stress-induced stretched-exponential time dependence of threshold voltage shift in InGaZnO thin film transistors

The experimental and modeling study of bias-stress-induced threshold voltage instabilities in amorphous indium-gallium-zinc oxide thin film transistors is reported. Positive stress results in a positive shift in the threshold voltage, while the transfer curve hardly moves when negative stress is induced. The time evolution of threshold voltage is described by the stretched-exponential equation, and the shift is attributed to the electron injection from the channel into interface/dielectric traps. The stress amplitudes and stress temperatures are considered as important factors in threshold voltage instabilities, and the stretched-exponential equation is well fitted in various bias temperature stress conditions.

Characterization of Transient Gate Oxide Trapping in SiC MOSFETs Using Fast $I$–$V$ Techniques

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown SiO2 and NO-annealed gate oxides have been studied using fast I-V measurements. These measurements reveal the full extent of the instability underestimated by dc measurements. Furthermore, fast measurements allow the separation of negative and positive bias stress effects. Postoxidation annealing in NO was found to passivate the oxide traps and dramatically reduce the instability. A physical model involving fast transient charge trapping and detrapping at and near the SiC/SiO2 interface is proposed.

Cycling Effect on the Random Telegraph Noise Instabilities of nor and nand Flash Arrays

The impact of program/erase (P/E) cycling on the random telegraph noise (RTN) threshold voltage instability of NOR and NAND flash memories is studied in detail. RTN is shown to introduce exponential tails in the distribution of the threshold voltage variation between two subsequent read operations on the cells. Tail height is shown to increase as a function of the stress levels, with a larger relative increase for the NAND case. The slope of the distribution instead remains nearly independent of the number of applied P/E cycles. This reveals that trap generation takes place according to the native trap distribution over the active area and means that the tail slope is a basic RTN parameter, depending on the cell process details for a fixed technology. These results are important for the design of the threshold voltage levels in multilevel nor and NAND technologies.

Modified Threshold Voltage Shift Model in a-Si:H TFTs Under Prolonged Gate Pulse Stress

The threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) instability of hydrogenated amorphous silicon thin film transistor under constant gate bias stress has been examined and modeled as a stretched-exponential equation previously. However, the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift (Delta V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) characteristic under prolonged gate pulsed stress, which also occurs in practical circuit operation, has not been well modeled so far. In this letter, we compared the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift property with existing models under gate pulse stress. For Delta V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> under prolonged stress, we found inaccuracies in the previous models and subsequently proposed a modified model, which can be applied to estimate V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift correctly for prolonged pulse stress of various duty ratios.

Stress-Induced Positive Charge in Hf-Based Gate Dielectrics: Impact on Device Performance and a Framework for the Defect

A Hf-based dielectric has been selected to replace SiON for CMOS technologies. When compared with SiON, Hf dielectrics can suffer from higher instability. Previous attentions were focused on electron trapping, and positive charging received less attention. The objective of this paper is to study the impact of positive charging on device performance and to provide a framework for the defect. Three components of threshold voltage instability Delta Vth are unambiguously identified for pMOSFETs, i.e., loop, loop-shift, and up-loop. The loop dominates Delta Vth at a relatively short time (< 1 s). After stressing for a longer time, the whole loop is shifted in the negative direction. Unlike the loop, the up-loop cannot readily be recharged after recovery. In addition to the generated interface states, three different types of positive charges are formed in the Hf-based stacks, i.e., cyclic positive charges (CPC), antineutralization positive charges (ANPC), and as-grown hole trapping (AHT). Each type of defect has its unique signatures and properties. CPC can repeatedly be charged and discharged by alternating the gate bias polarity. ANPC is more difficult to neutralize, whereas AHT is harder to charge. Both the generated interface states and the AHT saturate at longer stress time, but ANPC does not. ANPC reduces at higher measurement temperature, but CPC is insensitive to temperature. The relation between each type of defect and each component of Delta Vth is clarified.

Increase in oxide hole trap density associated with nitrogen incorporation at the SiO2/SiC interface

Nitrogen incorporation at the SiO2/SiC interface via high temperature nitric oxide annealing leads to the passivation of electrically active interface defects, yielding improved inversion mobility in the semiconductor. However, we find that such nitrided oxides can possess a larger density of hole traps than as-grown oxides, which is detrimental to the reliability of devices (e.g., can lead to large threshold voltage instabilities and to accelerated failure). Three different charge injection techniques are used to characterize this phenomenon in metal–oxide–semiconductor structures: x-ray irradiation, internal photoemission and Fowler–Nordheim tunneling. Some nitrogen-based atomic configurations that could act as hole traps in nitrided SiO2 are discussed based on first-principles density functional calculations.

Investigation of the Random Telegraph Noise Instability in Scaled Flash Memory Arrays

This paper investigates the main features of the random telegraph noise statistical instability in Flash memory arrays. The exponential tails introduced in the cumulative distribution of the threshold voltage variation between two subsequent read operations on the cells are shown to be preserved when the available statistics is increased. Large threshold voltage instabilities are therefore to be admitted, requiring the possibility for large random telegraph noise fluctuation amplitudes and the superposition of multi-trap random telegraph noise effects. Moreover, tails drift for increasing elapsed time between the compared read operations due to the activation of slower and slower traps in the random telegraph noise process, whose effect should be carefully considered in drawing reliability projections. Finally, the results for an early and an optimized NOR process are presented, showing non-negligible differences in their exponential tails behavior and revealing the existence of important parameters other than the technology node feature size having a significant impact on the random telegraph noise instability.

Direct observation of electrically active interfacial layer defects which may cause threshold voltage instabilities in HfO2 based metal-oxide-silicon field-effect transistors

We show that a Si∕HfO2 interfacial layer defect with an electron spin resonance spectrum similar to that of some E′ center variants responds to oxide bias consistent with an amphoteric defect. The spectrum is weakly orientation dependent indicating that the defect does not reside in a completely amorphous matrix. The defect’s spin lattice relaxation time is much shorter than that of conventional E′ centers suggesting that the defect involves some coupling of a Hf atom to a nearby oxygen deficient silicon dangling bond defect. This defect very likely plays an important role in widely reported instabilities in HfO2 based transistors.

The Effects of Drain-Bias on the Threshold Voltage Instability in Organic TFTs

In this letter, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied. By applying different drain biases to adjust the channel carrier concentration in linear mode, the threshold voltage shift was found to be proportional to the carrier concentration. The experimental data can be well quantitatively explained by the drain bias-stress theory developed for a-Si TFTs. The outcome gives the insight of the degradation mechanism of OTFTs and is important for the design of OTFT pixel circuit, OTFT analog amplifiers, or OTFT active loads.

Impacts of Fluorine Ion Implantation With Low-Temperature Solid-Phase Crystallized Activation on High- $\kappa$ LTPS-TFT

In this letter, fluorine ion implantation with low- temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> low-temperature poly-Si thin- film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> is achieved because 25% grain- boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric and fluorine preimplantation can simultaneously achieve low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ~ 1.32 V, excellent subthreshold swing ~0.141 V/dec, and high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</sub> current ratio ~1.98 times 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> .

Statistical Model for Random Telegraph Noise in Flash Memories

This paper presents a new physics-based statistical model for random telegraph noise in Flash memories. From the probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide, the model can explain the main features of the random telegraph noise threshold-voltage instability. The results on the statistical distribution of the threshold-voltage difference between two subsequent read accesses show good agreement between measurements and model predictions, even considering the time drift of the distribution tails. Moreover, the model gives a detailed spectroscopic analysis of the oxide defects responsible for the random telegraph noise, allowing a spatial and energetic localization of the traps involved in the threshold-voltage instability process.