Abstract
A model is presented to allow calculation of the bound states in the conduction band notch at the interface between the interfacial native GeO2 and high-κ dielectric layer in a Ge MOSFET gate stack. The notch represents a potential charge trapping site, which can induce threshold voltage instability. The model is applied to a three-dimensional structure, and the number of electrons or average occupancy of confined electrons in the notch is calculated. The effect of device physical and electrical parameters on the number of bound states and average occupancy of states in the notch is discussed. The significance of the confined charge in the notch and its effect on the threshold voltage shift in an 8-nm node Ge MOSFET is investigated. The main conclusion is that charge storage in this notch is insignificant at the relevant technology node.
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