Increase In On-resistance Research Articles

Source/Drain Engineering for High Performance Vertical MOSFET

In this paper, Source/Drain (S/i>/D) engineering for high performance (HP) Vertical MOSFET (V-MOSFET) in 3Xnm generation and its beyond is investigated, by using gradual S/i>/D profile while degradation of driving current (ION) due to the parasitic series resistance (Rpara) is minimized through two-dimensional device simulation taking into account for gate-induced-drain-leakage (GIDL). In general, it is significant to reduce spreading resistance in the case of conventional Planar MOSFET. Therefore, in this study, we focused and analyzed the abruptness of diffusion layer that is still importance parameter in V-MOSFET. First, for improving the basic device performance such as subthreshold swing (SS), ION, and Rpara, S/D engineering is investigated. The dependency of device performance on S/D abruptness (σS/D) for various Lightly Doped Drain Extension (LDD) abruptness (σLDD) is analyzed. In this study, Spacer Length (LSP) is defined as a function of σS/D. As σS/D becomes smaller and S/D becomes more abrupt, LSP becomes shorter. SS depends on the σS/D rather than the σLDD. ION has the peak value of 1750µA/µm at σS/D =2nm/dec. and σLDD=3nm/dec. when the silicon pillar diameter (D) is 30nm and the gate length (Lg) is 60nm. As σS/D becomes small, higher ION is obtained due to reduction of Rpara while SS is degraded. However, when σS/D becomes too small in the short channel devices (Lg =60nm and Lg =45nm), ION is degraded because the leakage current due to GIDL is increased and reaches IOFF limit of 100nA/µm. In addition, as σLDD becomes larger, larger ION is obtained in the case of Lg =100nm and Lg =60nm because channel length becomes shorter. On the other hand, in the case of Lg =45nm, as σLDD becomes larger, ION is degraded because short channel effect (SCE) becomes significant. Next, the dependency of the basic device performance on D is investigated. By slimming D from 30nm to 10nm, while SS is improved and approaches the ideal value of 60mV/Decade, ION is degraded due to increase of on-resistance (Ron). From these results, it is necessary to reduce Rpara while IOFF meets limit of 100nA/µm for designing S/D of HP V-MOSFET. Especially for the V-MOSFET in the 1Xnm generation and its beyond, the influence of the Rpara and GIDL on ION becomes more significant, and therefore, the trade-off between σS/D and ION has a much greater impact on S/D engineering of V-MOSFET.

High-voltage AlGaN/GaN HFETs by using graded gate field plates

High-voltage AlGaN/GaN heterostructure field-effect transistors (HFETs) with graded gate field-plate (FP) structures were fabricated to investigate the effectiveness of a linearly graded FP structure on current collapse. To improve the reproducibility of the FP structure manufacturing process, a simple process for a linearly graded SiO2 profile formation was developed. A HFET with a 23°-angle FP exhibited a significantly decreased on-resistance increase ratio of 1.16 after application of a drain bias of 600 V.

Suppression of Current Collapse of High-Voltage AlGaN/GaN HFETs on Si Substrates by Utilizing a Graded Field-Plate Structure

SUMMARY Current collapse of AlGaN/GaN heterostructure fieldeffect transistors (HFETs) formed on qualified epitaxial layers on Si substrates was successfully suppressed using graded field-plate (FP) structures. To improve the reproducibility of the FP structure manufacturing process, a simple process for linearly graded SiO2 profile formation was developed. An HFET with a graded FP structure exhibited a significant decrease in an on-resistance increase ratio of 1.16 even after application of a drain bias of 600 V.

Impact of Gate and Passivation Structures on Current Collapse of AlGaN/GaN High-Electron-Mobility Transistors under Off-State-Bias Stress

Using a dual-gate structure, we have investigated the impact of gate-stress position on the current collapse behavior of AlGaN/GaN high-electron-mobility transistors (HEMTs) without surface passivation. When the gate-bias stress under the off state was applied to the additional gate between the main gate and the drain electrode, we observed a marked increase in on-resistance (RON). On the other hand, the off-state stress on the main gate itself caused a decrease in drain saturation current as well as an increase in RON. The calculation of electric field at the AlGaN surface showed that the field peaks existed at the gate edges on both the drain and source sides, probably causing electron charging at the AlGaN surface near both gate-edge areas. These results indicated that the off-state gate stress induces “virtual gates” in the gate edges expanding in both the drain and source directions. The impacts of device structures on the current collapse have been characterized, using Schottky-gate HEMTs with and without surface passivation and metal–oxide–semiconductor (MOS) gate HEMTs. The surface passivation and MOS-gate structure was effective in mitigating current collapse, which was explained in terms of surface state density, electric field strength, and gate leakage current.

High Temperature Characteristics of Diamond SBDs

Because of the superior material properties of diamond, high performance in high-temperature power device application is demonstrated in both the computational and the experimental studies. A calculated Baliga limit of diamond Schottky barrier diode (SBD) based on 1D model indicates that an increase in on-resistance is highly expected within the high blocking voltage region and will be remarkable at high temperature conditions. Because of the high barrier height of diamond SBDs, the reverse leakage current is suppressed even at high temperatures. From the high-temperature stability test, stable interfaces of metal/diamond contact with constant Schottky barrier height have been confirmed. The SBD works for more than 1500 hrs at 400oC.

Short-Circuit Capability of SiC Buried-Gate Static Induction Transistors: Basic Mechanism and Impacts of Channel Width on Short-Circuit Performance

Fundamental short-circuit operations of silicon carbide static induction transistors with buried-gate structures (BGSITs) were experimentally clarified, with subsequent device simulations. The impacts of channel width and source length on short-circuit capabilities were investigated. In particular, a design concept of the channel width was proposed to improve the short-circuit energy without a serious increase in on-resistance. The maximum short-circuit capability of the fabricated BGSITs was 18 J/cm2 at room temperature, which shows excellent performance compared with that of conventional Si insulated-gate bipolar transistors.

Increase in Reverse Operation Limit by Barrier Height Control of Diamond Schottky Barrier Diode

Diamond is a promising material for high-power and low-loss semiconductor devices. However, the reported reverse blocking electric field of diamond-based power devices is as low as 2 MV/cm, and their performance is worse than ideal. We have developed reach-through-type Schottky barrier diodes (SBDs) with various Schottky barrier heights (SBHs) by changing metals. SBDs with high SBH show low leakage current and high operation limit of 3.1 MV/cm. This indicates that the reverse operation limit of diamond SBDs is determined not by leakage through defects but by carrier transport through the barrier. Reduction of specific on-resistance increases Baliga's figure of merit to 51 MW/cm2, which is tenfold higher than the Si limit.

High-Temperature Reliability Assessment of 4H-SiC Vertical-Channel JFET Including Forward Bias Stress

In this work, we report the most recent reliability results of the 1200-V SiC vertical-channel JFETs (VJFETs) under reverse and forward bias of the gate-source diode at temperatures up to 200 °C. The preliminary results indicate that continuous forward bias stress of the gate-source diode at 200 °C for 112 hours produced no observable change in the forward conduction or transient or reverse blocking characteristics of the vertical-channel JFET. This preliminary result suggests that devices based on this structure, such as the enhancement-mode (normally off) SiC VJFET, may not be effected by the recombination enhanced defect creation process and the associated increase in on-resistance, related to body-diode conduction in the SiC DMOSFET and the SiC lateral-channel depletion-mode JFET. Since the vertical-channel JFET has no body diode, no degradation is possible from the reverse conduction mode of operation.

A Model for Predicting On-Current Degradation Caused by Drain-Avalanche Hot Carriers in Low-Temperature Polysilicon Thin-Film Transistors

A model for predicting on-current degradation caused by drain-avalanche hot carriers in NMOS low-temperature polysilicon thin-film transistors (TFTs) is described. The amount of trapped charge caused by hot-carrier stress was estimated by using a model describing the lightly doped drain region as an imaginary TFT, and it was found that the amount of trapped charge saturates as voltage-stress time passes. Moreover, the on-resistance increase caused by the trapped charge could be expressed as a function of voltage-stress time (t) , stress drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d_str</sub> ), and stress drain voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d_str</sub> ), i.e., DeltaR <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> = I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d_str</sub> exp(-beta/ V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d_str</sub> ) At <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sup> . This function can be used to predict the on-current degradation of TFTs after a long time for various gate lengths, operation voltages, and crystallinities of polysilicon.

Effect of Buffer Layer Structure on Drain Leakage Current and Current Collapse Phenomena in High-Voltage GaN-HEMTs

High-voltage (> 400 V) GaN high-electron mobility transistors were fabricated using two types of heterostructures with different buffer layer structures. The buffer layer structure affected the crystal defect density in grown AlGaN/GaN heterostructure. The static on-resistance under low applied voltage was independent of the buffer layer structure because it has no influence on the 2-D electron-gas density. On the other hand, the drain leakage current through the grown layers and the dynamic on-resistance increase caused by the current collapse phenomena depended on the buffer layer structure. The leakage current was reduced by the AlN/n-GaN/AlN layers because of the potential barrier at the AlN/n-GaN interface and no-depletion of the n-GaN layer. In addition, the experimental results showed that the dynamic on-resistance was increased with the edge dislocation density and was not influenced by the screw dislocation density. From these results, it can be expected that edge dislocation is related to the electron trapping center, which must be reduced to suppress the current collapse phenomena.

Physical phenomena affecting performance and reliability of 4H–SiC bipolar junction transistors

The silicon carbide bipolar junction transistor (BJT) is attractive for use in high-voltage switching applications offering high-voltage blocking characteristics, low switching losses, and is capable of operating at current densities exceeding 300A/cm2. However, performance reliability issues such as degradation of current gain and on-resistance currently prohibit commercial production of 4H–SiC BJTs. This paper examines the physical mechanisms responsible for this degradation as well as the impact that these physical phenomena have on device performance. Results were obtained through the examination of several types of N–P–N BJT structures using various fabrication methodologies. Electron-beam induced current (EBIC) and potassium hydroxide (KOH) etching were used to characterize defect content in the material, before and after device current stress, when possible. It was found that Shockley stacking faults (stress-induced structures) associated with the forward voltage drift phenomenon in SiC bipolar diodes, also play a major role in the reduction of gain and an increase of on-resistance of the BJTs. However, results from some devices suggest that additional processes at the device periphery (edge of the emitter) may also contribute to degradation in electrical performance. Hence, it is essential that the sources of electrical degradation, identified in this paper, be eliminated for SiC BJTs to be viable for commercial scale production.

Impact of silicon nitride CESL on NLDEMOS transistor reliability

Aging of the linear drain current during OFF stress on a N-type lateral drain extended MOS is shown to be induced by the amorphous silicon nitride Contact Etch Stop Layer (CESL). A design of experiment on its PECVD conditions enables to demonstrate that the higher its Si-rich composition or at least of its interface, the higher the degradation. Supported by TCAD simulations, we propose a charge displacement model in the CESL that leads to the depletion of the extended drain region during stress explaining the on-resistance increase monitored by the linear drain current.

Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature

In this paper, we have investigated the electrical characteristics of power lateral double-diffused MOSFETs (LDMOSFETs) having different gate lengths (2.1–3μm) and drift lengths (6.6–12.6μm) in the temperature range 100–500K. The results of this study indicate that gate length and drift region length have a great effect on electrical characteristics, but they have little effect on temperature dependence. The specific on-resistance and the off-state breakdown voltage increase with temperature. The result shows that the specific on-resistance increases exponentially with the exponent 2.2 and, by contrast, the off-state breakdown voltage increases linearly with a slope of 100mV/K (drift region concentration of measured device: 2×1015cm−3). As a result, Ron/BV, known for a figure of merit of power device, increases with temperature.

On-Resistance Modulation of High Voltage GaN HEMT on Sapphire Substrate Under High Applied Voltage

The 620-V/1.4-A GaN high-electron mobility transistors on sapphire substrate were fabricated and the ON-resistance modulations caused by current collapse phenomena were measured under high applied voltage. Since the fabricated devices had insulating substrates, no field-plate (FP) effect was expected and the ON-resistance increases of these devices were larger than those on an n-SiC substrate even with the same source-FP structure. The dual-FP structure, which was a combination of gate FP and source FP, was effective in suppressing the ON -resistance increase due to minimization of the gate-edge electric field concentration. The ON-resistance after the applied voltage of 250 V decreased by twice that at low drain voltage by the dual-FP structure. Gallium nitride (GaN), high-electron mobility transistor (HEMT), high voltage, power semiconductor device.

Suppression of Dynamic On-Resistance Increase and Gate Charge Measurements in High-Voltage GaN-HEMTs With Optimized Field-Plate Structure

The dynamic on-resistance increase associated with the current collapse phenomena in high-voltage GaN high-electron-mobility transistors (HEMTs) has been suppressed by employing an optimized field-plate (FP) structure. The fabricated GaN-HEMTs of 600 V/4.7 A and 940 V/4.4 A for power-electronics applications employ a dual-FP structure consisting of a short-gate FP underneath a long-source FP. The measured on-resistance shows minimal increase during high-voltage switching due to increased electric-field uniformity between the gate and drain as a result of using the dual FP. The gate-drain charge Q gd for the fabricated devices has also been measured to provide a basis for discussion of the ability of high-speed switching operation. Although Q gd /A (A: active device area) was almost the same as that of the conventional Si-power MOSFETs, R on A was dramatically reduced to about a seventh of the reported 600-V Si-MOSFET value. Therefore, R on Q gd for 600-V device was reduced to 0.32 OmeganC, which was approximately a sixth of that for the Si-power MOSFETs. The high-voltage GaN-HEMTs have significant advantages over silicon-power MOSFETs in terms of both the reduced on-resistance and the high-speed switching capability.

950V, 8.7mohm-cm2 High Speed 4H-SiC Power DMOSFETs

AbstractFabrication and characteristics of high voltage, high speed DMOSFETs in 4H-SiC are presented. The devices were built on 1.2×1016 cm-3 doped, 6 mm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 8.7 mW-cm2 and a blocking voltage of 950 V were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by 35% observed at 300oC, when compared to the value at room temperature. This is due to a negative shift in MOS threshold voltage, which decreases the MOS channel resistance at elevated temperatures. This effect cancels out the increase in drift layer resistance due to a decrease in bulk electron mobility at elevated temperature, resulting in a temperature stable on-resistance. The device operation at temperatures up to 300 oC and high speed switching results are also reported in this paper.

1.8 kV, 10 mOhm-cm2 4H-SiC JFETs

AbstractFabrication and characteristics of high voltage, normally-on JFETs in 4H-SiC are presented. The devices were built on 5x1015 cm-3 doped, 12 μm thick n-type epilayer grown on a n+ 4H-SiC substrate. A specific on-resistance of 10 m Ω-cm2 and a blocking voltage of 1.8 kV were measured. Device characteristics were measured for temperatures up to 300oC. An increase of specific on-resistance by a factor of 5 and a decrease in transconductance were observed at 300oC, when compared to the value at room temperature. This is due to a decrease in bulk electron mobility at elevated temperature. A slight negative shift in pinch-off voltage was also observed at 300oC. The devices demonstrated robust DC characteristics for temperatures up to 300oC, and stable high temperature inverter operation in a power DC-DC converter application, using these devices, is reported in this paper.

1000-V, 30-A 4H-SiC BJTs with high current gain

This paper presents the development of 1000 V, 30A bipolar junction transistor (BJT) with high dc current gain in 4H-SiC. BJT devices with an active area of 3/spl times/3 mm/sup 2/ showed a forward on-current of 30 A, which corresponds to a current density of 333 A/cm/sup 2/, at a forward voltage drop of 2 V. A common-emitter current gain of 40, along with a low specific on-resistance of 6.0m/spl Omega//spl middot/cm/sup 2/ was observed at room temperature. These results show significant improvement over state-of-the-art. High temperature current-voltage characteristics were also performed on the large-area bipolar junction transistor device. A collector current of 10A is observed at V/sub CE/=2 V and I/sub B/=600 mA at 225/spl deg/C. The on-resistance increases to 22.5 m/spl Omega//spl middot/cm/sup 2/ at higher temperatures, while the dc current gain decreases to 30 at 275/spl deg/C. A sharp avalanche behavior was observed at a collector voltage of 1000 V. Inductive switching measurements at room temperature with a power supply voltage of 500 V show fast switching with a turn-off time of about 60 ns and a turn-on time of 32 ns, which is a result of the low resistance in the base.

Lateral polysilicon p +–p–n + and p +–n–n + diodes

Lateral polysilicon p +–p–n + and p +–n–n + diodes are fabricated and their electrical characteristics, such as ON-resistance, ideality factor and reverse current, are studied as a function of the polysilicon microstructure, the type and amount of doping in the lightly doped region and the length of the lightly doped region. Increasing the polysilicon grain size reduces the ON-resistance. The ON-resistance decreases while the reverse current increases with an increase in the amount of doping in their lightly doped region. The ON-resistance is higher and the reverse current is lower in diodes having p-type lightly doped regions. With an increase in the length of the lightly doped regions, the ON-resistance increases, while the reverse current does not change. The ideality factor does not depend upon the length of the lightly doped region, type of doping in this region and the grain size of polysilicon. The experimental observations are explained using a combination of field enhanced emission and a formulation that considers the effect of the grain-boundary segregation of dopants.

An implanted-emitter 4H-SiC bipolar transistor with high current gain

An epi-base, implanted-emitter, npn bipolar transistor which showed a maximum common emitter current gain (/spl beta/) of /spl sim/40, the highest current gain reported for BJT in any polytype of SiC has been experimentally demonstrated in 4H-SiC. The forward drop was /spl sim/1 V at forward current density of 50 A/cm/sup 2/. The current gain decreases hence specific on-resistance increases with increasing temperature. The negative temperature coefficient of /spl beta/ makes the device attractive for paralleling and for preventing thermal runaways.