Gate Work Function Research Articles

Design and simulation of triple metal double-gate germanium on insulator vertical tunnel field effect transistor

In this paper, a novel Triple metal double gate germanium on insulator vertical TFET is proposed and investigated by using SILVACO ATLAS TCAD tool. Gate metal work-function engineering is used to overcome the problem of low ON-current, high OFF-current, high average subthreshold swing and low ION/IOFF ratio which are present in single material double gate TFET. By modulating the values of metal gate work-functions, the performance of the device is improved. The low band-gap material and vertical tunneling concept also increase the steepness of subthreshold slope as well as ON-current of the device. Further the effects of channel length and gate to source overlap thickness on the device are also analysed to get optimum device dimensions for obtaining the improved performance results. The vertical stacking of source, channel and drain also consumes less space as compared to the conventional TFETs. So, the considerable good performance of this proposed device makes it suitable as an attractive choice for ultra-low power applications.

Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

In this paper, for the first time, we have investigated the DC and analog/RF performance metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using HfxTi1−xO2 high-k material in gate stack to improve subthreshold characteristics. The 3-D device performance of single-k, dual-k, and hybrid spacer is compared without spacer dielectric, and DC characteristics are presented. In this move, it is noticed that the device attains the highest ION/IOFF ratio of ~109 compared to ~105 due to an increase of effective gate length by fringing fields with spacer dielectric. Moreover, to evaluate and understand the nanostructure performance comparison is made between Junctionless (JL), Accumulation (ACC), and Inversion (INV) modes. The device exhibits excellent DC characteristics with ION/IOFF ratio of ~109, subthreshold swing (SS) of ~61.8 mV/dec, drain induced barrier lowering of (DIBL < 25 mV/V), and Vth ~ 0.36 V in all three modes with dual-k spacer. Moreover, the impact of device dimensional and process parameters such as gate length (LG), fin width (FW), fin height (FH), temperature (T), and work function variations on switching characteristics (ION/IOFF) are extracted and studied. The device performance acknowledges that Moore’s law can be validated even in 3 nm nodes to continue further scaling.

Analytical Modeling and Performance Analysis of Surface Potential for Junctionless MOSFET

The advancement in semiconductor technology requires small devices with low power consumption. This paper presents an analytical modeling of surface potential for junctionless MOSFET. Parabolic approximation is utilized to find out the surface potential. The effect of device parameter variation on surface potential and electric field has been studied. The variation in gate work function has been investigated for surface potential. Moreover, the consequence of variations in device parameters like drain bias, gate length ratio, radius of silicon pillar and doping concentration are also inspected. It is found that present device shows an excellent behaviour for future VLSI chips. The analytical results are matched with the TCAD results which validates the model.

Reducing Ambipolar Conduction in a Graphene Tunneling Field Effect Transistor (GTFET) via Bandgap Engineering

Tunneling field effect devices suffer from two main problems comprised of low on-state current and intrinsic ambipolar conduction. In the present work, we propose a graphene tunneling field effect transistor (GTFET), that uses graphene nanoribbon (GNR) with a narrow bandgap (0.1 eV) in the source and another GNR with a wider bandgap (0.7 eV) in the drain and channel regions. This structure improves on-state current, reduces ambipolar conduction and increases the ION/IOFF. We also examine the effect of important parameters including doping concentration, drain voltage, bandgap, gate work function, and dielectric thickness on the electrical performance of the proposed device. Moreover, we compare the digital and analog performance of the proposed structure with two other GTFETs having GNRs with wide or narrow bandgaps across the source, channel and drain regions. The proposed GTFET shows a very high on-state to off-state current ratio (1E11) and thus, it is superior for digital applications. In addition, by calculating the transconductance (g m ) and output conductance (g d ) we find that the proposed structure has a higher intrinsic gain compared to the two other structures. Therefore, it is more suitable for analogue applications in comparison with two other structures.

Impact of auxiliary gate work function on boosting electrical performance of a gate-all-around field effect transistor with emphasis on the scaling behavior

To recuperate subthreshold characteristics and short channel endurance of gate-all-around field effect transistors (GAA-FETs) by scaling, we incorporate an auxiliary gate with an appropriate work function close to the source side of a conventional circular GAA(CGAA) transistor in our simulation study. The CGAA electrical characteristics have been calibrated against a 22 nm IBM sample. Based on our simulation results, utilizing an auxiliary gate with higher work function material in the proposed structure (AuxG-GAAFET) leads electron energy sub-bands to be more split out. This reduces electron concentration in the channel and thus the leakage current is decreased along with subthreshold slope (SS). Furthermore, the proposed AuxG-GAAFET shows better ION/IOFF current ratio, lower threshold voltage roll-off, better subthreshold slope (SS) and better drain induced barrier lowering (DIBL) factor caused by scaling. For this, utilizing an appropriate auxiliary gate can be among promising methods for deep transistor scaling in the future.

Negative capacitance enables GAA scaling VDD to 0.5 V

We present a TCAD simulation of the negative capacitance gate-all-around (NCGAA) field-effect transistor with the 3-D Ginzburg-Landau-Khalatnikov Model. The baseline device is based on the 2020 IRDS Table, and the mobility model is calibrated to account for ballistic transport and to match the “1.5 nm node” IRDS on-current requirement. The NC parameters are extracted from experimental C-V data. The NC-GAA shows reduction in the off current by one order of magnitude and a 40% on-current boost. If the gate work function is shifted to align the NC-GAA’s off-current with the IRDS high performance requirement, it is shown that NC-GAA can achieve the on-current and VDD requirement of every node through the “0.7 eq node,” which is the last node predicted in the 2020 IRDS Table. Furthermore, NC-GAA can even achieve a “0.5 eq node,” which is three additional nodes beyond the baseline “1.5 nm node.” We also show that these benefits are retained over a varying set of ferroelectric parameters.

A Charge Plasma Based Label Free Biomolecule Detector Using SiGe-Heterojunction Double Gate Tunnel FET

To overcome the random dopant fluctuations (RDFs) and high thermal budget problems faced by normally doped Tunnel Field Effect Transistor (TFET) devices, charge plasma SiGe-heterojunction double gate TFET is utilized to design a label free biosensor. The performance of proposed biosensor is analyzed for different values of dielectric constant (k), charge density (both positive and negative), gate work function and cavity dimensions. These parameters alter the electric properties of the biosensor which help in the detection process. Their effect on the drain current, electric field, surface potential, sub-threshold swing (SS), ION/IOFF ratio, and electron tunneling rate (ETR) of the device is also discussed. Furthermore, the drain current sensitivity of the proposed biosensor is analyzed and it is found that a maximum sensitivity of 1.13 × 1010 is obtained for dielectric constant k = 12. The proposed biosensor is implemented by carrying out two-dimensional device simulations using the Silvaco ATLAS tool.

Charge Plasma-Based Phosphorene Tunnel FET Using a Hybrid Computational Method

In this paper, a charge plasma-based phosphorene double-gate tunnel FET (CP-BPDGTFET) is investigated. A hybrid simulation technique involving both atomistic and technology computer-aided design (TCAD) has been used to simulate the device characteristics. First, the density functional theory has been used to simulate phosphorene electrical characteristics (monolayer to few-layer, including armchair and zigzag directions). The parameters such as band gap and effective mass obtained using an atomistic simulator tool are exported into Sentaurus TCAD to simulate the device characteristics. The drain current characteristics are calibrated for conventional double gate phosphorene tunnel FET with non-equilibrium Green's function results. The DC characteristics of the proposed device are studied. The device performance is analysed by varying the device parameters such as gate length (Lg), spacer length (Ls), and gate workfunction (ϕm). Based on the study, an optimised device is designed, and its characteristics are obtained. The optimised device offers an on-current value of 405 µA/µm, SS = 79 mV/dec, Ion/Ioff = 1.13 × 106 for 30 nm gate length. It establishes that CP-BPDGTFET is a suitable candidate for energy-efficient circuit applications.

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Short channel effects (SCEs) along with mobility degradation has a great impact on CMOS technology below 100 nm. These effects can be overcome by using gate and channel engineering techniques which will improve mobility of the charge carriers, thus eventually improving drain current and trans-conductance of the device. In this work, the speed of operation for DG MOSFET is improved by reducing the channel length where dual-material gate-stack is deployed to avoid the drain-induced barrier lowering (DIBL) and hot carrier effects. In the presented device, the metal closer to the source and drain has higher and lower work function, respectively which causes a significant decrement in the peak electric field at the drain side and so the SCEs. The carrier mobility is also increased due to enhanced electric field in the channel, near the source, caused by higher work function gate material which, in turn, increases the MOSFET’s driving current. The screening effect reducing SCEs and an increment in the acceleration of the charge carriers in the channel are mainly attributed due to higher and lower threshold voltage found near the source and drain, respectively.

Analytical and Compact Modeling Analysis of a SiGe Hetero-Material Vertical L-Shaped TFET

This paper deals with the development of a novel 2-D analytical modeling of heterojunction vertical L-shaped tunnel FET for characterisation of surface potential and drain current. The compact analysis includes the properties of dual modulation effect with the numerous efforts to predict the characteristics of current and to discuss the method of device improvement. The dual modulation effect is used to regulate the biasing voltage at both the junction of source and drain of surface potential to determine the tunneling width. A 2-D Poisson equation is solved for the proposed model by using parabolic approximation method with constant electric field which are used to determine the effect of SiGe mole-fraction, gate-drain biasing potential, dielectric constant of gate oxide, drain doping concentration, metal gate work-function and different binary compound material on the device surface potential. Most importantly, a new channel surface potential expression is derived that can forecast the effect of drain and gate biasing. The derived model results are compared with those of simulated results in order to evaluate the validity of electrical parameter model.

Dual Metal Double Gate Ge-Pocket TFET (DMG-DG-Ge-Pocket TFET) with Hetero Dielectric: DC &amp; Analog Performance Projections

This work exclusively illustrates dual-metal double gate Ge pocket tunnel field effect transistor (DMG-DG-Ge pocket TFET) with hetero gate dielectric. This structure includes dual-metal gate and hetero-dielectric as well. Extensive TCAD simulation analysis is carried out to illustrate how the device transfer characteristics changes in different regions with respect to various parameters such as, the work-function of tunneling gate and auxiliary gate variations, lengths ratio of tunneling gate and auxiliary gate, and the dielectric constants of homo/hetero dielectrics involved. Here, optimization of dual metal gate work-function is done along with dual gate metal length ratio. To optimize the device behavior hetero gate dielectric HfO2 and SiO2 are considered over the source-channel interface and channel-drain interface, respectively. The enhanced device transfer characteristics obtained are explained and verified with the energy band diagram and tunneling length. The reported device structure achieves ION/IOFF = 5.05 × 1011 and sub-threshold slope (SS) as 15.9425 mV/decade along with the reduced ambipolar current. An increase in ION/IOFF ratio by the order of four as compared to Ge-pocket TFET, is reported with reasonably high ON current for sub 0.5 V supply. This enables the device for low power applications. In addition to this, for the complete analog and RF characterization of the proposed device structure, transconductance, parasitic capacitance, cut-off frequency, intrinsic delay, energy-delay product, transconductance generation factor etc. are also illustrated in detail here. Further, the energy efficiency of the device is also analyzed and justifies for its low power high-speed applications.

Work function optimization for enhancement of sensitivity of dual-material (DM), double-gate (DG), junctionless MOSFET-based biosensor

In this work, the impact of gate material work function on the sensitivity of dual-material, double-gate, junctionless MOSFET ( $$DMDG-JL-MOSFET$$ )-based biosensor has been studied. To enhance the sensitivity of the biosensor, optimization of gate work functions has been done through Sentaurus TCAD simulator. With the immobilization of biomolecules in the cavity at different value of work function of gate metal 1 (M1) and gate metal 2 (M2), i.e., WF1 and WF2, enhancement in sensing metrics (change in threshold voltage $$S_{V{\rm th}}$$ and $$I_{ON}$$ / $$I_{OFF}$$ ratio) is observed. The enhancement in sensitivity is profound in source-side gate (M1) work function (WF1) optimization as compared to drain-side gate (M2) work function (WF2) optimization. Sensitivity of 90 mV is observed in source-side gate work function optimization which is $$\sim$$ 89% more than the sensitivity of 23 mV which is achieved in drain-side gate work function optimization for a fixed concentration and dielectric constant of biomolecules. It has also been noted that the proposed structure exhibits $$\sim 90\%$$ higher sensitivity than the single-material, dual-gate, junctionless MOSFET ( $$SMDG-JL-MOSFET$$ ) biosensor. Results showcase that the optimization of gate metal work functions enhances the sensitivity of the biosensor.

Effects of BOX thickness, silicon thickness, and backgate bias on SCE of ET-SOI MOSFETs

In this work, we investigate the effect of BOX (Buried OXide) and silicon thickness on the SCE (Short-Channel Effects) of ET-SOI (Extremely Thin Silicon-on-Insulator) MOSFETs. It is found that the minimum channel length Lmin is only moderately sensitive to the BOX thickness but strongly dependent on the silicon thickness. For a given threshold voltage, the choice of gate work function in combination with the backgate bias also plays a role on Lmin. Reverse bias mitigates SCE while forward bias aggravates SCE. An empirical expression of Lmin in terms of silicon thickness is given.

Design of a triple pocket multi-gate material TFET structure for low-power applications

In this paper we propose a triple-pocket multi-gate material TFET (TP-TFET) device structure for a low-power and high-performance circuit design. The proposed device structure integrates the good features of both the conventional MOSFET and tunnel FET. This is achieved through three doped pockets and dual work-function gate material on near the source–channel junction. In the proposed device, the ON state conduction mechanism is dominated by an over-the-barrier thermal diffusion of carriers, thereby offering a high-value drive current. On the other hand, the subthreshold conduction mechanism is dominated by the tunnelling of carriers, thereby incurring a very small leakage current and offering a small subthreshold slope. We use 2D TCAD device simulations for the analysis of the TP-TFET and its comparison with the existing pocketed-heterogate TFET (PHG-TFET). We observe that the proposed TFET offers the average subthreshold slope (SSavg) of 2.85 mV dec−1 and ON current of ∼230 µA µm−1 as compared to the existing PHG-TFET, which offers SSavg of 44.91 mV dec−1 and I ON = ∼62 µA µm−1. Further, some benchmark circuits are implemented using these devices. A ring oscillator designed using the TP-TFET shows approximately a 6× higher frequency as compared to that designed using the PHG-TFET. The power delay product of the NAND gate and NOR gate obtained using these devices differ by approximately 3× to 20× as the supply voltage is decreased from 1.0 to 0.5 V.

Low-Power Vertical Tunnel Field-Effect Transistor Ternary Inverter

In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations.

Design analysis of Gate-All-Around nanowire tunnel field effect transistor

In this paper the effect of physical design parameters on electrical characteristics of cylindrical tunnel field effect transistor has been studied by a numerical simulator. Simulations are performed on technology node varied from 40 nm to 20 nm based on which the results have been extracted at an optimized 30 nm channel length by employing different substrate material with assorted gate oxide material. Deviation in transfer characteristics have also been observed by varying thickness of gate oxide and work function of gate. Comparisons of different materials with oxides brought out nitride with silicon as the better combination, with ON current of about 1µA/µm and OFF current less than 1 pA/µm. This work gives an understanding of the involvement of physical parameters in the operation of the device.

Impact of back gate work function for enhancement of analog/RF performance of AJDMDG Stack MOSFET

In this work, the impact of back gate work function on analog/RF performance of Asymmetric Junctionless Dual Material Double Gate MOSFET with high K gate Stack (AJDMDG Stack MOSFET) has been studied. The impact of back gate work function on analog/RF parameters like drain current (ID), transconductance (gm), transconductance generation factor (TGF), intrinsic gain, output resistance (rout), cut-off frequency, maximum frequency of oscillation (fmax) etc. have been studied through TCAD device simulator. The results reveal that an improvement in analog/RF performance has been achieved by choosing a low value work function of the back gate.

Design and Analysis of Dual-Metal-Gate Double-Cavity Charge-Plasma-TFET as a Label Free Biosensor

In this paper, the bipolar nature of tunnel field effect transistor (TFET) has been utilized for the first time for the identification of biomolecules. C harge plasma concept has been employed to achieve simpler process of fabrication, lower cost and to overcome random dopant fluctuation. The focus of this work is to utilize both ON and ambipolar state of dual metal gate double cavity charge plasma TFET (DMG-DC-CPTFET) biosensor for sensing the biomolecules. Consideration of cavities at both tunneling junctions, it is possible to sense different kinds of biomolecules simultaneously. Gate workfunction engineering has been employed to improve sensitivity and to minimize the OFF state current of the proposed biosensor. High-k gate dielectric is used to achieve maximum ON current. The variation in electrical characteristics like energy band, surface potential and the electric field resulting from the presence of charged and neutral biomolecules in the cavities has been studied. The proposed model offers maximum sensitivity of $2.88\times 10\,\,^{{11}}$ ( $2.88\times 10^{13}$ %) under ON state and $1.37\times 10^{{7}}$ ( $1.37\times 10^{9}$ %) under ambipolar state.

Performance enhancement of junctionless silicon nanotube FETs using gate and dielectric engineering

The silicon nanotube field effect transistor (FET) is a tubular structure and has an inner gate and outer gate to control the channel. In this paper, the performance of a junctionless silicon nanotube FET is optimized using inner and outer gate engineering through 3D numerical TCAD simulations. The performance of the optimized devices is enhanced in terms of ON current (ION), OFF current (IOFF), and $$\frac{{I_{{{\text{ON}}}} }}{{I_{{{\text{OFF}}}} }}$$ ratio. Appropriate work function and gate dielectric choices are suggested for the inner and outer gates to obtain optimized devices. The lowest IOFF and highest $$\frac{{I_{{{\text{ON}}}} }}{{I_{{{\text{OFF}}}} }}$$ ratio are obtained for devices with high inner and outer gate permittivity along with low inner and outer gate work function. Also, the highest ION is obtained for the device with the highest inner and outer gate dielectric permittivity with low outer and inner gate work function. The device optimized for ION (98.6% increase compared to reference device) with the corresponding IOFF better than the reference device can be used for high-power applications.

Gate Work Function Engineered Trigate MOSFET with a Dual-Material Bottom Gate for Biosensing Applications: a Dielectric-Modulation Based Approach

Mathematical model development of a Dielectric-Modulated Dual Material Trigate MOSFET with a dual material bottom gate has been introduced for application as a biosensor for detection of biomolecules like enzymes, cell, DNA etc. With solution of 3-D Poisson’s equation, electrical features of the proposed device have been acquired and corresponding shift in the device features due to change in permittivity, charge etc. by the biomolecules implies the type of biomolecule introduced in the nanogap. Further simulation results from Atlas corroborate the analytical results.