Abstract
The advancement in semiconductor technology requires small devices with low power consumption. This paper presents an analytical modeling of surface potential for junctionless MOSFET. Parabolic approximation is utilized to find out the surface potential. The effect of device parameter variation on surface potential and electric field has been studied. The variation in gate work function has been investigated for surface potential. Moreover, the consequence of variations in device parameters like drain bias, gate length ratio, radius of silicon pillar and doping concentration are also inspected. It is found that present device shows an excellent behaviour for future VLSI chips. The analytical results are matched with the TCAD results which validates the model.
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