Performance improvement of spacer engineered n-type SOI FinFET at 3-nm gate length

Abstract

In this paper, for the first time, we have investigated the DC and analog/RF performance metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using HfxTi1−xO2 high-k material in gate stack to improve subthreshold characteristics. The 3-D device performance of single-k, dual-k, and hybrid spacer is compared without spacer dielectric, and DC characteristics are presented. In this move, it is noticed that the device attains the highest ION/IOFF ratio of ~109 compared to ~105 due to an increase of effective gate length by fringing fields with spacer dielectric. Moreover, to evaluate and understand the nanostructure performance comparison is made between Junctionless (JL), Accumulation (ACC), and Inversion (INV) modes. The device exhibits excellent DC characteristics with ION/IOFF ratio of ~109, subthreshold swing (SS) of ~61.8 mV/dec, drain induced barrier lowering of (DIBL < 25 mV/V), and Vth ~ 0.36 V in all three modes with dual-k spacer. Moreover, the impact of device dimensional and process parameters such as gate length (LG), fin width (FW), fin height (FH), temperature (T), and work function variations on switching characteristics (ION/IOFF) are extracted and studied. The device performance acknowledges that Moore’s law can be validated even in 3 nm nodes to continue further scaling.