Abstract
In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations.
Highlights
Over the past several decades, CMOS dimensions have been continuously scaled down to make switching speed faster and integration density increasing in accordance with Moore’s Law [1]
In this study, the new ternary CMOS (T-CMOS) which consists of the vertical tunnel FETs is introduced and analyzed using TCAD simulations with the calibrated model parameters
As contrast to the previously reported T-CMOS, the proposed T-CMOSVF is utilizing only the tunneling currents generated at sourceto-channel and source-to-drain junctions to form the three different VOUT states
Summary
Over the past several decades, CMOS dimensions have been continuously scaled down to make switching speed faster and integration density increasing in accordance with Moore’s Law [1]. In an inverter, as n-/p-type devices are operated in the VGS range where only source-to-drain tunneling occurs, VOUT is determined by the resistance difference between them as a voltage divider and the VOUT with a stable third half VDD state (V3rd) can be formed if both the devices have the equivalent tunneling current. Considering that the T-CMOSVF is intentionally designed to have the wide flat leakage current region regardless of VGS before source-to-channel tunneling occurs at VGS > 0.4V, it is remarkable that the proposed device can be operated at VIN = 0.6 V, which is the lower operation voltage than that of the previous T-CMOS with VIN > 1V for the proper ternary operations [27]. Ternary inverters can decrease the number of transistors by designing ternary arithmetic circuits compared to binary logics and thereby power consumption can be reduced despite of the power dissipation by the third state formation
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