Gate Size Research Articles

Selective ion transport through hydrated micropores in polymer membranes.

Ion-conducting polymer membranes are essential in manyseparation processes and electrochemical devices, including electrodialysis1, redox flow batteries2, fuel cells3 and electrolysers4,5. Controlling ion transport and selectivity in these membranes largely hinges on the manipulation of pore size. Although membrane pore structures can be designed in the dry state6, they are redefined upon hydration owing to swelling in electrolyte solutions. Strategies to control pore hydration and a deeper understanding of pore structure evolution are vital for accurate pore size tuning. Here we report polymer membranes containing pendant groups of varying hydrophobicity, strategically positioned near charged groups to regulate theirhydration capacity and pore swelling. Modulation of thehydrated micropore size (less thantwo nanometres) enables direct control over water and ion transport across broad length scales, as quantified by spectroscopic and computational methods. Ion selectivity improves in hydration-restrained pores created by more hydrophobic pendant groups. These highly interconnected ion transport channels, with tuned pore gate sizes, show higher ionic conductivity and orders-of-magnitude lower permeation rates of redox-active species compared with conventional membranes, enabling stable cycling of energy-dense aqueous organic redox flow batteries. This pore size tailoringapproach provides a promising avenue to membranes with precisely controlled ionic and molecular transportfunctions.

Impact of Runner Size, Gate Size, Polymer Viscosity, and Molding Process on Filling Imbalance in Geometrically Balanced Multi-Cavity Injection Molding.

The injection molding process is one of the most widely used methods for polymer processing in mass production. Three critical factors in this process include the type of polymer, injection molding machines, and processing molds. Polypropylene (PP) is a widely used semi-crystalline polymer due to its favorable flow characteristics, including a high melt flow index and the absence of a need for a mold temperature controller. Additionally, PP exhibits good elongation and toughness, making it suitable for applications such as box hinges. However, its tensile strength is a limitation; thus, glass fiber is added to enhance this property. It is important to note that the incorporation of glass fiber increases the viscosity of PP. Multi-cavity molds are commonly employed to achieve cost-effective and efficient mass production. The filling challenges associated with geometrically balanced layouts are well documented in the literature. These issues arise due to the varying shear rates of the melt in the runner. High shear rate melts lead to high melt temperatures, which decrease melt viscosity and facilitate easier flow. Consequently, this results in an imbalanced filling phenomenon. This study examines the impact of runner size, gate size, polymer viscosity, and molding process on the filling imbalanced problem in multi-cavity injection molds. Tensile bar injection molding was performed using conventional injection molding (CIM) and microcellular injection molding (MIM) techniques. The tensile properties of the imbalanced multi-cavity molds were analyzed. Flow length within the cavity served as an indicator of the filling imbalance. Additionally, computer simulations were conducted to assess the shear rate's effect on the runner's melt temperature. The results indicated that small runner and gate sizes exacerbate the filling imbalance. Conversely, glass fiber-filled polymer composites also contribute to increased filling imbalance. However, foamed polymers can mitigate the filling imbalance phenomenon.

Competition between rate strengthening and gravitational acceleration induces stick-slips of inclined granular flow

This study conducted experiments on dry granular mass released on an inclined flume. The periodic acceleration and deceleration of the flow, that is, the stick-slip phenomenon, was observed during the experiments. To investigate the stick-slip motion mechanism, numerical simulations were conducted with the inclusion of the shear-strengthening μ(I)-rheology into the elasto-plastic models of granular flow. The stick-slip phenomenon was captured naturally without the modification of the empirical friction law. The results revealed that the competition between the rate strengthening implemented by the μ(I)-rheology and the gravitational acceleration along the inclined plane induces stick-slips. By considering the experimental results in combination with the simulation results, the effects of the particle size, gate size opening, surface roughness, and frictional parameters of μ(I)-rheology on the stick-slip phenomenon were elucidated.

The influence of mold design and process parameters on dimensional shrinkage of perfluoroalkoxy alkane injection molding parts

AbstractIn mass production, injection molding plays a vital role in manufacturing various parts with complex settings. As perfluoroalkoxy alkane (PFA) injection‐molded products are widely used in immersion system, dimensional quality needs more attention. However, there is limited research on the dimension defects of PFA injection‐molded products. This study focused on the influence of mold design and process parameters on PFA part shrinkage, using mold flow simulation and orthogonal testing separately. Several gate locations and sizes were simulated to minimize shrinkage in mold design. Displacements varied with gate locations, and shrinkage decreased with larger gate sizes. The Taguchi method analyzed process parameters' impact on shrinkage. The results indicated that the injection rate had the most significant effect on the shrinkage of tube length, while melt temperature, holding pressure, and screw speed affected the shrinkage of tubes' outside diameter. Different flow directions exhibited variance in shrinkage. Using max–min normalization, the two shrinkage values reached 0.00972, whereas the smallest value obtained in the orthogonal experiment was 0.1545 in run 3. Thus, optimizing mold design and process parameters were two effective methods to reduce shrinkage. This study reduced shrinkage and improved the quality of PFA injection molding parts for semiconductor systems.

A [92.4] FO4(1V), [53.71] Eu(1V) 4-bit absolute-value detector

With the development of modern computers, the integration of chips is getting higher and higher, and as the computing power increases, the energy consumption of chips is also increasing. Therefore, designing and optimizing low-latency and low-energy chips are the goals of many researchers today. At the same time, 4-bit absolute value detector are one of the most basic and important circuits for data storage and processing in chips. This paper designs a 4-bit absolute value detector circuit using Complementary Metal Oxide Semiconductor (CMOS) transistors that can take the absolute value of the input 4-bit signed number and compare it with the threshold value. And it includes the design of its absolute value conversion module and comparator module. By optimizing the circuit structure, the number of logic gates is reduced. By calculating the minimum delay on the critical path, logic gate size and other parameters, the power consumption of the circuit is reduced by adjusting the delay. In conclusion, this paper research can help further optimize the development of chip design industry.

Tuning Gate Potential Profiles and Current-Voltage Characteristics of Polymer Electrolyte-Gated Transistors by Capacitance Engineering.

We demonstrate that the transfer characteristics of electrolyte-gated transistors (EGTs) with polythiophene semiconductor channels are a strong function of gate/electrolyte interfacial contact area, i.e., gate size. Polythiophene EGTs with gate/electrolyte areas much larger than the channel/electrolyte areas show a clear peak in the drain current vs gate voltage (ID-VG) behavior, as well as peak voltage hysteresis between the forward and reverse VG sweeps. Polythiophene EGTs with small gate/electrolyte areas, on the other hand, exhibit current plateaus in the ID-VG behavior and a gate-size-dependent hysteresis loop between turn on and off. The qualitatively different transport behaviors are attributed to the relative sizes of the gate/electrolyte and channel/electrolyte interface capacitances, which are proportional to interfacial area. These interfacial capacitances are in series with each other such that the total capacitance of the full gate/electrolyte/channel stack is dominated by the interface with the smallest capacitance or area. For EGTs with large gates, most of the applied VG is dropped at the channel/electrolyte interface, leading to very high charge accumulations, up to ∼0.3 holes per ring (hpr) in the case of polythiophene semiconductors. The large charge density results in sub-band-filling and a marked decrease in hole mobility, giving rise to the peak in ID-VG. For EGTs with small gates, hole accumulation saturates near 0.15 hpr, band-filling does not occur, and hole mobility is maintained at a fixed value, which leads to the ID plateau. Potential drops at the interfaces are confirmed by in situ potential measurements inside a gate/electrolyte/polymer semiconductor stack. Hole accumulations are measured with gate current-gate voltage (IG-VG) measurements acquired simultaneously with the ID-VG characteristics. Overall, our measurements demonstrate that remarkably different ID behavior can be obtained for polythiophene EGTs by controlling the magnitude of the gate-electrolyte interfacial capacitance.

Flight dynamics of aircraft incorporating the semi-aeroelastic hinge

Aircraft like the Boeing 777-X use on-ground folding wingtips to meet the airport gate size restriction while increasing the aspect ratio during flight to reduce induced drag. A recent concept of aircraft design is to utilise in-flight floating wingtips as a means of load alleviation, which is known as semi-aeroelastic hinge (SAH). This device allows wingtips to be released during manoeuvre and severe gusts to alleviate wing loads, while locking the wingtips during cruise to maintain an optimum aerodynamic shape. This paper develops a flight mechanics model incorporating flexible wings to study the influence of the SAH device on multiple aspects of aircraft flight dynamics. The dynamic responses of the aircraft to gusts and control surface inputs are computed and compared for various hinge and wingtip configurations and release times. It was found that the gust load measured from the wing with free hinge configuration was approximately 40% lower compared to that of the fixed hinge case. It is also shown that when the SAH is released, it can significantly reduce an aircraft's roll damping and the frequency of the short-period mode, leading to higher roll and pitch rates. Furthermore, it shows that the transient responses following the wingtip release will exacerbate the responses induced by gusts, and greater load alleviation can be achieved by manipulating the hinge release time for each gust length. Finally, a step input of the elevator during the hinge release was found to be beneficial for enhancing the gust load alleviation.

Design and optimization of a 16-bit spike detector based on 90nm CMOS technology

To deeply understanding of brain function, the rapid and accurate extracting relevant signals during brain operation has become increasingly important. As our understanding of brain function advances, the ability to extract relevant signals quickly and accurately becomes increasingly crucial. Therefore, a 16-bit spike detector has been designed to detect neural signals. Since a 4-bit absolute value detector is a critical module of the 16-bit spike detector, this paper presents a design for a 4-bit value comparator using a chain adder and a comparator. Two methods, changing the supply voltage and changing the gate size, were utilized to reduce power consumption, and it was found that changing the supply voltage method was more effective. Additionally, the circuits layout was designed for simulation to enhance the authenticity and reliability of the results. Currently, brain-computer interface technology remains a widely discussed topic in the field of neuroscience, and the speed and accuracy of neural signal processing continue to be critical issues that need to be addressed.

A New Design of A 6-Bit Absolute Value Detector by Using Both VDD Scaling and Sizing to Optimize

The presented paper focuses on the development and optimization of a 6-bit absolute value detector, a crucial digital block in encoder and decoder applications. The primary objective is to minimize energy consumption while maintaining a delay no greater than 1.5 times the minimum delay. The optimization process combines logical effort theory with gate sizing and voltage scaling techniques. Firstly, gate sizes are adjusted while keeping VDD constant, achieving a 73% reduction in energy consumption, reaching a delay constraint of 1.5 times the minimum delay. Secondly, VDD scaling is explored without altering gate sizes, resulting in a 40% reduction in energy consumption, reaching the minimum energy consumption point. Finally, gate sizing and VDD scaling are combined, yielding a remarkable 79% reduction in total energy consumption, with a supply voltage of 0.835 volts. These optimization strategies bridge a research gap in 6-bit absolute value detectors, significantly enhancing energy efficiency and offering valuable insights for intricate digital signal processing scenarios. The findings showcase the effectiveness of combining logical effort theory with gate sizing and voltage scaling to achieve substantial energy savings while meeting stringent delay constraints.

Consumption Analysis and Optimization Strategies for Four-Bit Absolute-Value Detectors

As embedded systems, communication systems, and neurology research continue to advance, the demand for high-performance components in digital circuits has risen. Simultaneously, there is a growing need for low-energy consumption. In this paper, Four-Bit Absolute-Value Detectors, as crucial components in digital circuits, have garnered significant attention for their role in achieving energy efficiency. This paper embarks on a comprehensive exploration, commencing with the fundamentals of circuit theory, circuit topologies, and circuit styles. Through extensive calculations and comparative studies, this paper conduct a thorough analysis of the factors influencing energy consumption in these circuits. The study reveals that various parameters have a substantial impact on energy consumption. To mitigate this, the author proposes multiple strategies, including gate size optimization, supply voltage optimization, and the selection of appropriate circuit styles. The significance of this study lies in providing foundational insights into the energy optimization of Four-Bit Absolute-Value Detectors. By investigating the interplay between gate sizes, supply voltage, path length, capacitance load, and circuit topology, this paper offer a holistic perspective on energy-efficient design.

Characterization and modeling of Single Event Transient propagation through standard combinational cells

Analysis of Single Event Transient (SET) effects is an important step in the design of radiation-hardened integrated circuits for space missions. Because the simulation of SET effects in a complex design would be very time-consuming, appropriate SET models are required to simplify and speed up the SET analysis. In this paper, we demonstrate an approach for deriving an analytical SET propagation model from the simulation-based characterization of standard cells. We have performed detailed characterization of standard combinational cells designed in IHP's 130 nm CMOS technology, using Cadence Spectre simulations. The simulation results have shown that significant SET broadening may occur across short combinational paths composed of up to ten logic gates, and supply voltage and temperature variations may enhance the SET broadening. By fitting the simulation results, an analytical model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model expresses the propagated SET pulse width in terms of gate's size factor, load capacitance, supply voltage and temperature. Using the proposed model allows for estimating the SET pulse width across any combinational path composed of characterized standard cells. The model was verified on selected combinational paths, and the average relative error with respect to simulations was 6.4 %.

A Converse for Fault-tolerant Quantum Computation

As techniques for fault-tolerant quantum computation keep improving, it is natural to ask: what is the fundamental lower bound on space overhead? In this paper, we obtain a lower bound on the space overhead required for ϵ-accurate implementation of a large class of operations that includes unitary operators. For the practically relevant case of sub-exponential depth and sub-linear gate size, our bound on space overhead is tighter than the known lower bounds. We obtain this bound by connecting fault-tolerant computation with a set of finite blocklength quantum communication problems whose accuracy requirements satisfy a joint constraint. The lower bound on space overhead obtained here leads to a strictly smaller upper bound on the noise threshold for noise that are not degradable. Our bound directly extends to the case where noise at the outputs of a gate are non-i.i.d. but noise across gates are i.i.d.

Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors

Total-ionizing-dose (TID) effects are evaluated in back-gated IGZO thin-film transistors irradiated under different gate biases. Negative-bias irradiation leads to worst-case degradation of TID response in these devices, primarily as a result of enhanced charge trapping in the SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> overlayer. The relatively small peak transconductance decrease after irradiation illustrates that IGZO transistors are much less sensitive to interface-trap buildup and other instabilities due to hydrogen release and transport than amorphous Si thin film transistors examined previously. The TID response of devices with different gate sizes is also investigated. No significant geometry dependence is observed, which is promising for future scaling down of the technology.

A branch-and-price algorithm for the airport gate assignment problem considering the trade-off between robustness and efficiency

In this paper, a novel objective for the airport gate assignment problem which considers the trade-off between robustness and operational efficiency in a unified dimension is developed. A task-based two-phase model is established, where the branch-and-price framework is embedded in the first stage. A set partitioning model is developed, where a series of aircrafts assigned to the same gate of a certain type are defined as a gate plan. The pricing subproblem is also decomposed into three parallel subproblems according to the gate size to account for the heterogeneity of the gates. Each gate plan is allocated to a physical gate in order to minimize the utilization of remote gates in the second stage. The pulse algorithm with two acceleration strategies, that generates a lower bound matrix in reverse order and applies path combination, is used to solve the pricing subproblems. Finally, extensive computational experiments are conducted to demonstrate the high performance of the proposed model, especially for large-scale instances.

Analytical Parasitic Resistance and Capacitance Models for Nanosheet Field-Effect Transistors

We developed analytical compact models of parasitic resistance and capacitance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> ) for nanosheet field-effect transistors (NSFETs) with metal contact structures. The proposed model accurately captures the number of sheets, sheet geometry, gate, source, drain, and contact sizes. The parasitic resistance model generated in each region was modeled using the transmission line method (TLM) and the spread resistance model. The parasitic capacitance model was modeled using the conformal mapping method based on the distribution of the electric field. The developed models were validated by changing the structural parameters. The proposed models were implemented in Berkeley short-channel IGFET model (BSIM)-common multi-gate (CMG) to enable circuit performance prediction. With our proposed model, we can accurately predict the circuit performance of NSFETs, capturing the recent scaling trends and process variations in the proposed NSFET.

Analysis of Channel length, Gate length and Gate position Optimization of III-Nitride/β-Ga2O3 Nano-HEMT for High-Power Nanoelectronics and Terahertz Applications

This research article reports the investigation of performance optimization of the field-plated and recessed gate III-Nitride nano-HEMT on β-Ga2O3 substrate. The optimization is done for channel length, gate length and suitable gate position in order to achieve a better DC and RF characteristics for high power and THz applications. The breakdown voltage and frequency characteristics of HEMTs are typically traded off. However, the proposed III-Nitride nano-HEMT grown over β-Ga2O3 substrate incorporating an optimal channel length, gate size, and suitable gate position exhibit improved breakdown voltage characteristics without sacrificing high-frequency properties. The III-nitride HEMT comprising of 250 nm channel length, 20 nm gate length, and gate position of 120 nm from source and 110 nm from drain exhibited the improved breakdown voltage characteristics and superior RF properties. The major factor contributing to this outcome is an improved lattice compatibility of substrate material with the buffer. This study intends to advance a thorough understanding of a breakthrough III-Nitride HEMT grown on β-Ga2O3 substrate, thereby facilitating further research in this state-of-the-art technology.

Task-Based Parallel Programming for Gate Sizing

Physical synthesis engines need to embrace all available parallelism to cope with the increasing complexity of modern designs and still offer high quality of results. To achieve this goal, the involved algorithms need to be expressed in a way that facilitates fast execution time across a range of computing platforms. In this work, we introduce a task-based parallel programming template that can be used for speeding up timing and power optimization. This approach utilizes all available parallelism and enables significant speedup relative to custom multithreaded approaches. Task-based parallelism is applied to all parts of the optimization engine covering also parts that are traditionally executed serially for preserving maximum timing accuracy. Using Taskflow as the parallel programming and execution engine, we achieved a speedup of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.7\times $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.8\times $ </tex-math></inline-formula> for gate sizing optimizations on the ISPD13 benchmarks with marginal extra leakage power relative to state-of-the-art multithreaded gate sizers. This result was supported by two dynamic heuristics that restrict the number of examined gate sizes and simplify local timing updates. Both heuristics tradeoff additional runtime reduction with marginal leakage power increases.

P‐2.30: Design and Fabrication of an Optical Path Folding Pancake Virtual Reality Head‐mounted Display

Metaverse has been going viral across the globe, and virtual reality head‐mounted displays (VR‐HMDs) as the basic infrastructure and entrance to cater to this evolution of social interaction are showing rapid development recently. Pancake optics based on optical path folding provides the feasibility of VR‐HMDs in the form of glasses and is wide recognition. The pancake system has become the current mainstream owing to its large exit pupil diameter (EPD), high resolution, novel compact, and lightweight. Owing to the use of polarization elements, the birefringence in the lens will change the polarization state of the light, resulting in uneven brightness and stray light, seriously reducing the optical performance of the system, so it is necessary to control the birefringence of the lens. In this study, we proposed a pancake system based on a 2.1‐inch LCD display which achieves 10 mm EPD at 11 mm, diagonal field of view (FOV) of 96°, overall length (OAL) of the system less than 20 mm, and support diopter adjustment from ‐7D to ‐1D. The residual birefringence of the lens can be effectively suppressed in four stages: 1) controlling the thickness ratio between the center and the edge of the lens during the optical design, 2) setting a reasonable position and size of the injection gate and cooling system during the mold design process, 3) adopting reasonable injection parameters during the precision injection molding process and 4) eliminating the birefringence of the lens with the lens annealing process. Ultra‐precision machining and correction of the mold cores have been employed to achieve high surface accuracy and low birefringence of the lens. The optomechanical design, assembly, and adjustment process are discussed. Finally, the prototype of the pancake system is experimentally tested, and the results demonstrate pretty well.

Experimental study of venting efficiency of salinity current

ABSTRACT The dam is one of the most prominent hydraulic constructions on the world. Sediment flows into dam reservoirs because of human involvement in the dam catchment region, eventually affecting its functional storage. Density currents are a key feature of sedimentation. The use of bottom outflow gates to preserve the reservoir’s usable volume is one approach of mitigating the effects of sedimentation. This could have an effect on the quality of the water as it exits the dam. The purpose of this research was to see how well salt current from lock exchanges was vented at different levels and outlet gate sizes. Based on the latest study’s experiments, this is the highest venting efficiency when the location of outlets is in the quarter of the bottom of the dam. The output concentration will be equal to the average concentration of the concentrated input current, which is the best height for installing the outlet gates, based on the maximum venting efficiency demonstrated in the recent study’s experiments, which may be described as the best height for the turbidity current outlet gate. Discharge efficiency increases when the intake concentration is lower.

A 93.56 FO4(1V), 141.36 Eu(1V) 4-bit Absolute-Value Detector

With the development of technology and The Times, the industry has higher and higher requirements for chip performance. Using better circuit design to achieve this goal has become the direction of researchers today. The 4-bit absolute value detector is one of the most important and basic circuits in computer storage and data processing. The effective improvement of its performance will greatly promote the improvement of processing efficiency in the whole chip industry. This project is to design a circuit of a 4-bit absolute value detector. The main functions it implements are it can get the absolute value of 2’s complement, then compare the 3-bit absolute value with a 3-bit threshold value. This paper first divides the design into three parts: absolute module, comparison module and other small modules. Minimize the delay by exploring the critical path and changing the gate size. Finally, through theoretical calculation and optimization, the optimal scheme designed in this paper is determined. The results of this paper will be helpful to the further development of related industries.