Abstract
Analysis of Single Event Transient (SET) effects is an important step in the design of radiation-hardened integrated circuits for space missions. Because the simulation of SET effects in a complex design would be very time-consuming, appropriate SET models are required to simplify and speed up the SET analysis. In this paper, we demonstrate an approach for deriving an analytical SET propagation model from the simulation-based characterization of standard cells. We have performed detailed characterization of standard combinational cells designed in IHP's 130 nm CMOS technology, using Cadence Spectre simulations. The simulation results have shown that significant SET broadening may occur across short combinational paths composed of up to ten logic gates, and supply voltage and temperature variations may enhance the SET broadening. By fitting the simulation results, an analytical model for estimating the SET pulse broadening and shrinking caused by individual logic gates has been derived. The proposed model expresses the propagated SET pulse width in terms of gate's size factor, load capacitance, supply voltage and temperature. Using the proposed model allows for estimating the SET pulse width across any combinational path composed of characterized standard cells. The model was verified on selected combinational paths, and the average relative error with respect to simulations was 6.4 %.
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