Characterization of Single Event Transient Effects in Standard Delay Cells

Abstract

Standard delay cells (SDCs) are commonly used for timing synchronization in digital designs. Due to skewed transistor sizing, the SETs induced in SDCs may be stretched during propagation through the cell, thus increasing the soft error rate. In this work, the simulation analysis of Single Event Transient (SET) effects in 130 nm SDCs is presented. The results have shown that the SETs induced in SDCs may be up to 1.46 ns wide, which is more than twice the width of SETs in other standard logic cells, for the same simulation settings. As the conventional gate-level SET mitigation techniques are not effective against long SETs, we have investigated two hardening solutions for SDCs: (i) complete duplication with a guard gate, and (ii) partial duplication with a guard gate applied only to the most sensitive inverters in the SDC. Both solutions can reduce significantly the generated SET pulse width, with the delay overhead of less than 250 ps. The estimated area overhead per cell is around 115 % for complete duplication and 80 % for partial duplication.