Gate Length Ratio Research Articles

Experimental analysis of combined side weir-gate located on a straight channel

Flow measurement and control in open channel system for lateral flow is important to support the system management. The flow characteristics of combined side weir-gate are complicated due to changes in flow conditions along the side weir-gate section. Experimental investigation of the flow characteristics of both weir and sluice gates is crucial for predicting the flow through a combined side weir-gate structure. Although weir-gate structures are widely used for frontal flow in hydraulic structures, the same is not true for lateral flows. In this study, 650 laboratory tests were conducted to determine the flow characteristics of combined side weir-gate for subcritical flow, and the experimental results were analyzed to determine the effect of these characteristics and weir-gate geometry on discharge capacity. Interaction factor of combined side weir-gate is a function of the upstream Froude number, the ratio of gate opening to upstream flow depth, the ratio of distance between the top of the sluice gate and the weir crest to gate opening, the ratio of weir and gate length to upstream flow depth, and the ratio of weir and gate length to main channel width. Consequently, more discharge is passed through combined side weir-gate compared to side weir and sluice gates. The empirically derived equations for the discharge of combined side weir-gate show good compatibility with the experimental data.

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm technology node SOI p-channel step-FinFET and compares with that of a conventional FinFET (c-FinFET). For the first time we have investigated the impact of various dimensional parameters like Gate Length (LG), Fin width (Wfin1 and Wfin2, Wfin = fixed), Fin height (Hfin1 and Hfin2, Hfin = fixed) and Fin-width ratio on the performance of c-FinFET and step-FinFET devices. These FinFET structures have been designed and simulated in Cogenda Visual TCAD under certain boundary conditions and the performance has been analyzed. The electrical parameters such as ON-current (ION), OFF-current (IOFF), Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vt) roll-off, Transconductance (gm) and Transconductance Generation Factor (TGF) are extracted. It is observed that short channel effects (SCEs) can be controlled by reducing Wfin1, decreasing major fin height (Hfin1) and increasing Gate length (LG) (14 nm to 20 nm). It is noticed that there is a significant improvement in ION/IOFF ratio from 1.01 × 104 to 1.41 × 105 with respect to increased channel length, SS of 76.68 mV/decade to 67.8 mV/decade and excellent DIBL of 55 mV/V in c-FinFET. For the proposed step-FinFET at LG = 16 nm there is improved DIBL of 85 mV/V compared to the c-FinFET, which can be further improved up to 64.63 mV/V by decreasing the Hfin1/Hfin2 ratio (4 to 0.25). The parametric analysis concludes that step-FinFET is more susceptible to SCEs in terms of DIBL, Vt roll-off as compared to the c-FinFET. This work considers LG = 16 nm for analysing the dimensional variation effect on both the devices. In contrast c-FinFET is more preferable than the proposed device at lower technology nodes.

Temperature dependence of the strain of the AlGaN barrier layer under the gate in AlGaN/AlN/GaN HFETs

By a combination of electrical measurement, the Debye model and the basic theory of polarization, the strain of AlGaN barrier layer underneath the gate in two AlGaN/AlN/GaN HFETs at the same ratio of gate length (LG) to source-drain distance (LSD) but with different dimensions is investigated at temperatures from 300 ​K to 450 ​K. It is found that temperatures have important influence on this strain. Furthermore, the temperature dependence of the strain is found related to device dimensions, a phenomenon that can be explained by the Ohmic contact metal atoms diffusion nearby the Ohmic electrode and lattice mismatch underneath the gate electrode. This study is conducive to understanding the effect of temperatures on the polarization Coulomb field (PCF) scattering, which has been verified to be a significant scattering mechanism affecting the performance of AlGaN/AlN/GaN HFETs.

Comparison of ratio of gate length to gate-drain distance influences on source access resistance of AlGaN/AlN/GaN HFETs at different temperatures

In this work, two AlGaN/AlN/GaN heterostructure field-effect transistors (HFETs) with different ratios of gate length (LG) to gate-drain distance (LGD) were used to compare the effects of ratio of LG to LGD on the source access resistance (RGS) at 300 K, 350 K, and 400 K. The results showed that the ratio of LG to LGD had a significant effect on RGS at the above-mentioned each temperature, which can be attributed to the polarization Coulomb field (PCF) scattering. In addition, the effects of the ratio of LG to LGD on RGS in the two AlGaN/AlN/GaN HFETs prepared in this work were different at different temperatures. This indicated that elevated-temperature performance of AlGaN/AlN/GaN HFETs can be improved by optimizing the ratio of LG to LGD based on PCF scattering.

Analytical Modeling and Performance Analysis of Surface Potential for Junctionless MOSFET

The advancement in semiconductor technology requires small devices with low power consumption. This paper presents an analytical modeling of surface potential for junctionless MOSFET. Parabolic approximation is utilized to find out the surface potential. The effect of device parameter variation on surface potential and electric field has been studied. The variation in gate work function has been investigated for surface potential. Moreover, the consequence of variations in device parameters like drain bias, gate length ratio, radius of silicon pillar and doping concentration are also inspected. It is found that present device shows an excellent behaviour for future VLSI chips. The analytical results are matched with the TCAD results which validates the model.

Analytical Modeling of Threshold Voltage for Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET

This paper presents, analytical modeling of surface potential,threshold voltage and DIBL for a Dual-Metal Double-Gate Gate-All-Around (DM-DG-GAA) MOSFET considering the parabolic approximation of surface potential. Poisson’s three-dimensional (3D) charge density equation has been solved by using proper boundary conditions to formulate the surface potential throughout the channel length. In this work, two gate metals of distinct work functions are used for gate electrode to create a step profile in channel potential. The potential step profile in surface potential reduces the SCEs in DM-DG-GAA MOSFET. The developed surface potential model is further considered to formulate the threshold voltage (Vth)model by using an effective conductive path and Fermi potential difference. The modeled threshold voltage is further used to find the Drain Induced Barrier Lowering (DIBL) effect. The threshold voltage and the DIBL are discussed with different values of device physical parameters like gate oxide (sio2) thickness, gate length ratio, channel thickness, and screening gate work function. This paper compares the SCEs of DM-DG-GAA MOSFET with Dual-Gate Gate-All-Around (DG-GAA) MOSFET and the results showing that DM-DG-GAA MOSFET offering better short channel characteristics than DG-GAA MOSFET. The model results are verified with simulation results generated from 3D device simulator ATLAS from SILVACO.

An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications

A small-signal radio-frequency (RF) parameters extraction model along with analog/RF and linearity distortion performance analysis are realized for virtually doped (VD) recessed source/drain dopingless junctionless transistor (Re S/D DLJLT) via 3-D device simulations. A simple and accurate RF non-quasi-static (NQS) model is developed to directly extract the extrinsic and intrinsic parasitic components through Y-parameters in OFF and ON-state respectively. Furthermore, direct comparison of DC, analog/RF, linearity figure of merits (FOMs), and Y-parameter extractions are made with recessed source/drain junction transistor (Re S/D JT) with identical threshold voltage (Vth) and device dimensions at GHz frequency range. Virtual doping, due to charge-plasma (CP) concept, provides N+ source/drain (S/D) regions by choosing a most convenient metal work function (WF = 3.9 eV; Hafnium) at S/D. Re S/D provides reduced series resistance without an increase in gate-drain Miller capacitance leading to improved drive current. In addition, the present device uses an intrinsic channel and does not require to be doped at S/D resulting in dopingless junctionless transistor (DLJLT). For both devices, gate length (L) is taken as 30 nm, which separated into control gate (L1) and screen gate (L2) and 3-D simulations are carried out by varying control to screen gate length ratios (CSLR) to obtain optimum results. Obtained results disclose that Re S/D DLJLT provides considerably improved performances in terms of DC, analog/RF, linearity, transient, and small-signal admittance parameters over Re S/D JT due to improved drive current and reduced short channel effects (SCEs). Accordingly, for high-performance RF applications, Re S/D DLJLT may be preferred over Re S/D JT due to significantly enhanced cut-off frequency (up to 0.399 THz) and maximum oscillation frequency (up to 1.226 THz).

Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.

2-D analytical modeling of drain and gate-leakage currents of cylindrical gate asymmetric halo doped dual material-junctionless accumulation mode MOSFET

This paper reports a physics-based analytical model for the cylindrical-gate (CG) asymmetric halo doped graded-channel (GC) dual-material (DM) junctionless-accumulation-mode (JAM) MOSFETs by incorporating both the effects of gate material engineering and channel engineering on the device characteristics. Poisson’s equation has been solved using the superposition technique with appropriate boundary conditions. The minimum central potential concept has been used to derive the threshold voltage model. The drain and gate currents have been modeled by including the effects of gate induced drain leakage (GIDL) and gate leakage currents, respectively. The performance parameters of the proposed CG-GCDM JAM MOSFETs have been compared with those of the CG-DM and CG-GC JAM-MOSFETs to show that the proposed structure has enhanced reliability against short channel effects (SCEs), hot carrier effects (HCEs) and various leakage currents (GIDL and gate leakage) for various control-to-screen gate length ratios. The proposed modeled results have been validated by comparing them with numerical data obtained by using a 3D commercial TCAD simulator.

Impact of two gate oxide with no junction metal oxide semiconductor field effect transistor- an analytical model

Abstract An analytical model based on physics is used to describe the potential distribution, horizontal electric field, and drain current of Two Gate Oxide with no junction MOSFET (TOX-NOJ-MOSFET) was investigated for cylindrical shape structure. The Poisson equation is used to derive the expression for cylindrical coordinate system which relies on parabolic approximation method. The combination of high k two gate oxide stack and junctionless transistor with Dual material Double gate structure performs a major role to diminish the short channel effects, propelled to increase the ION current (10−5A/μm) and decrease the leakage current IOFF of 10−14 A/μm to enhance ION/IOFF ratio to 109. To ensure the scalability and responsiveness of the system numerical simulations have been performed with various bias voltages and gate length ratios using Synopsys TCAD software and the results were well matched with analytical solutions.

Design and Analysis of Nanoscaled Recessed-S/D SOI MOSFET-Based Pseudo-NMOS Inverter for Low-Power Electronics

In this paper, a comparative analysis of nanoscaled triple metal gate (TMG) recessed-source/drain (Re-S/D) fully depleted silicon-on-insulator (FD SOI) MOSFET has been presented for the design of the pseudo-NMOS inverter in the nanometer regime. For this, firstly, an analytical modeling of threshold voltage has been proposed in order to investigate the short channel immunity of the studied device and also verified against simulation results. In this structure, the novel concept of backchannel inversion has been utilized for the study of device performance. The threshold voltage has been analyzed by varying the parameters of the device like the ratio of metal gate length and the recessed-source/drain thickness for TMG Re-S/D SOI MOSFET. Drain-induced barrier lowering (DIBL) has also been explored in terms of recessed-source/drain thickness and the metal gate length ratio to examine short channel effects (SCEs). For the exact estimation of results, the comparison of the existing multimetal gate structures with TMG Re-S/D SOI MOSFET has also been taken under study in terms of electrostatic performance, i.e., threshold voltage, subthreshold slope, and on-off current ratio. These structures are investigated with the TCAD numerical simulator from Silvaco ATLAS. Furthermore, for the first time, TMG Re-S/D FD SOI MOSFET-based pseudo-NMOS inverter has been designed to observe the device performance at circuit levels. It has been found that the device offers high noise immunity with optimum switching characteristics, and the propagation delay of the studied circuit is recorded as 0.43 ps.

Gate-All-Around Charge Plasma-Based Dual Material Gate-Stack Nanowire FET for Enhanced Analog Performance

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current ( ${I}_{\text {D}}$ ), transconductance ( ${g}_{m}$ ), transconductance gain factor ( ${g}_{m}/{I}_{D}$ ), output conductance ( ${g}_{\text {ds}}$ ), early voltage ( ${V}_{\text {AE}}$ ), intrinsic gain ( $A_{\text {v}}$ ), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, ${L}_{G}$ , and ratio of control gate length to total gate length, $L_{\text {M1}}/{L}_{G}$ . This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidates for analog application with cost-effective fabrication.

Analysis of power consumption and delay of an inverter circuit using TMJLSRG MOSFET for the design of digital integrated circuit

This paper represents delay and power analysis of an inverter using a triple-material junctionless surrounding gate MOSFET (TMJLSRG) to design integrated circuit. TCAD tools have been used for the purpose of simulation. The delay and power consumption are the vital design metrics to design the circuit in nano level. In this work, the variation of power consumption has been reported for different values of power supply voltage VDD and channel length. Delay is also reported with respect to VDD .Moreover, power consumption has been reported for the gate engineered device for different ratio of gate length. The results are satisfactory to design low power and high speed digital integrated circuit using TMJLSRG MOSFET.

Design and optimization analysis of dual material gate on DG-IMOS

An impact ionization MOSFET (IMOS) is evolved for overcoming the constraint of less than 60 mV/decade sub-threshold slope (SS) of conventional MOSFET at room temperature. In this work, first, the device performance of the p-type double gate impact ionization MOSFET (DG-IMOS) is optimized by adjusting the device design parameters. The adjusted parameters are ratio of gate and intrinsic length, gate dielectric thickness and gate work function. Secondly, the DMG (dual material gate) DG-IMOS is proposed and investigated. This DMG DG-IMOS is further optimized to obtain the best possible performance parameters. Simulation results reveal that DMG DG-IMOS when compared to DG-IMOS, shows better ION, ION/IOFF ratio, and RF parameters. Results show that by properly tuning the lengths of two materials at a ratio of 1.5 in DMG DG-IMOS, optimized performance is achieved including ION/IOFF ratio of 2.87 × 109 A/μm with ION as 11.87 × 10−4 A/μm and transconductance of 1.06 × 10−3 S/μm. It is analyzed that length of drain side material should be greater than the length of source side material to attain the higher transconductance in DMG DG-IMOS.

Exploring the short channel characteristics and performance analysis of DMDG SON MOSFET

A two-dimensional (2-D) analytical model for dual-material double gate (DMDG) Silicon-on-Nothing (SON) MOSFETs is developed to study the effect of variation of both the surface potential and threshold voltage on short channel effects (SCEs). Two dimensional (2-D) Poisson's equation with proper boundary conditions has been solved considering the parabolic potential approximation. The model includes the calculations of threshold voltage, electric field and subthreshold swing. The impact of variation of the device parameters such as gate length ratios, gate metal work functions on the performance of the device has been examined and the results are compared to that of dual-material double gate (DMDG) Silicon-on-Insulator (SOI) MOSFETs. The calculated results obtained have been validated with the numerical simulation data obtained from ATLAS, a 2-D device simulator from SILVACO.

Analytical modeling of subthreshold characteristics by considering quantum confinement effects in ultrathin dual-metal quadruple gate (DMQG) MOSFETs

In this work, analytical models of subthreshold characteristics for an ultrathin dual-metal quadruple gate MOSFET have been developed by considering the quantum confinement effects. The 2D Schrödinger’s equation has been solved analytically to obtain the threshold voltage and subthreshold current of ultrathin dual-metal quadruple gate MOSFET with minimum cross-section of 3nm×3nm. The inversion charge density at the threshold condition is obtained by considering minimum sub-band energy levels with a square potential well approximation for a two dimensional (width and height) carrier confinement. The subthreshold characteristics have been analyzed by varying different device parameters like channel cross-section, gate length ratio, gate metal work functions and gate oxide thickness. Further, the effect of 2D charge carrier confinement on drain induced barrier lowering (DIBL) has also been discussed using the threshold voltage model. The proposed models are validated against the numerical simulation results obtained from 3D ATLAS device simulator.

2-D analytical modeling of subthreshold current and subthreshold swing for ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

In this paper, the subthreshold behavior of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs has been analyzed by means of subthreshold current and subthreshold swing. The surface potential based formulation of subthreshold current and subthreshold swing is done by solving the 2-D Poisson’s equations in the channel region using parabolic approximation method. The dependence of subthreshold characteristics on various device parameters such as gate length ratio, Ge mole fraction, peak doping concentration, projected range, straggle parameter etc. has been studied. The modeling results are found to be well matched with the simulation data obtained by a 2-D device simulator, ATLAS™, from SILVACO.

Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET

The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current ([Formula: see text]), the transconductance ([Formula: see text]), the transconductance generation factor ([Formula: see text]/[Formula: see text]) and the intrinsic gain ([Formula: see text]Ro). The drain induced barrier lowering (DIBL) of the devices is compared. The RF analysis is performed using the non quasi static (NQS) approach. We consider the intrinsic gate to source capacitances ([Formula: see text]), the intrinsic gate to drain capacitance ([Formula: see text]), the intrinsic gate to source resistances ([Formula: see text]), the intrinsic gate to drain resistance ([Formula: see text]), the transport delay ([Formula: see text]), the unity current gain cut-off frequency ([Formula: see text]) and the max frequency of oscillation ([Formula: see text]) for the RF comparisons. A single stage amplifier is also implemented using the devices for a circuit comparison.

Analytical threshold voltage modeling of ion-implanted strained-Si double-material double-gate (DMDG) MOSFETs

Two dimensional threshold voltage model of ion-implanted strained-Si double-material double-gate MOSFETs has been done based on the solution of two dimensional Poisson’s equation in the channel region using the parabolic approximation method. Novelty of the proposed device structure lies in the amalgamation of the advantages of both the strained-Si channel and double-material double-gate structure with a vertical Gaussian-like doping profile. The effects of different device parameters (such as device channel length, gate length ratios, germanium mole fraction) and doping parameters (such as projected range, straggle parameter) on threshold voltage of the proposed structure have been investigated. It is observed that the subthreshold performance of the device can be improved by simply controlling the doping parameters while maintaining other device parameters constant. The modeling results show a good agreement with the numerical simulation data obtained by using ATLAS™, a 2D device simulator from SILVACO.

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.