Proposal of Charge Plasma Based Recessed Source/Drain Dopingless Junctionless Transistor and its Linearity Distortion Analysis for Circuit Applications

Abstract

Linearity and intermodulation distortion (IMD) analysis examined major reliability issues that arise due to the non-linear behavior of the devices in analog/RF circuit applications. In this paper, by means of virtually doped (dopingless), a distinctive influence of charge-plasma (CP) is proposed on novel dual metal gate (DMG; control and screen gate) recessed source/drain (Re S/D) transistor; envisaged as recessed source/drain dopingless junctionless transistor (Re S/D DLJLT). Re S/D structure diminishes series resistance without any accretion of the gate-drain Miller capacitance resulting in a better drive current (ION). DC and analog characteristics have been further improved by adopting CP conception for induction of N+ S/D region owing to favorably well-chosen metal work function electrodes. The main intent of this paper is to appraise the linearity and IMD performance characteristics of the Re S/D DLJLT using 2-D numerical calculations and scrutinize the distinction with recessed source/drain junction transistor (Re S/D JT) with identical dimensions. Device linearity parameters comprise of transconductance (Gm1) and its higher order coefficients (Gm2 and Gm3), second and third order voltage and input intercept point (VIP2, VIP3, and IIP3) third order IMD, and 1 − dB compression point (1 − dBCP) which are based on possible structural and control to screen gate length ratios (CSLR) variations in both devices. The influences of parametric modifications on linearity Figure of merits (FOMs) explore optimum bias point by investigating optimum structural with CSLR variations. The detailed investigation of linearity FOMs of the impact on different device engineering has been carried out. The obtained outcomes divulge that proposed device delivers appreciably enhanced linearity FOMs as compared to Re S/D JT.