Abstract

In this paper, a gate-all-around (GAA) charge plasma-based dopingless dual material gate nanowire FET is proposed (CP-DM). This structure is further explored by adding gate-stack (high-k + SiO2) feature (CP-GS-DM). In these dopingless structures, source/drain is induced using a charge plasma concept by an appropriate selection of work functions for source/drain electrodes. The dopingless devices offer low thermal budget with easier fabrication steps and reduced random dopant fluctuations effect. Both the dopingless structures are investigated for analog performance, and results are compared with those obtained from the GAA junctionless dual material (JL-DM) gate and the JL gate-stacked DM gate (JL-GS-DM), respectively. The charge plasma-based dopingless devices when compared with their JL counterpart show improvement in drive current ( ${I}_{\text {D}}$ ), transconductance ( ${g}_{m}$ ), transconductance gain factor ( ${g}_{m}/{I}_{D}$ ), output conductance ( ${g}_{\text {ds}}$ ), early voltage ( ${V}_{\text {AE}}$ ), intrinsic gain ( $A_{\text {v}}$ ), drain-induced barrier lowering, and subthreshold slope. Thus, dopingless structures show enhanced analog performance with reduced short channel effects. The charge plasma based dopingless gate stacked dual material gate (CP-GS-DM) shows the best performance of all the structures. The analysis is further carried out for investigating the device design parameters effect on performance, namely, total gate length, ${L}_{G}$ , and ratio of control gate length to total gate length, $L_{\text {M1}}/{L}_{G}$ . This way dopingless charge plasma-based devices incorporate DM and GS features that make these devices interesting and reliable candidates for analog application with cost-effective fabrication.

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