Gate Junctionless Research Articles

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

Correlation of Core Thickness and Core Doping with Gate & Spacer Dielectric in Rectangular Core Shell Double Gate Junctionless Transistor

The impression of gate dielectric and spacer dielectric on the performance of rectangular core shell double gate junctionless transistor (RCS-DGJLT) using extensive simulations is studied. The RCS-DGJLT brings captivating response in terms of the performance of the device. The effect of gate dielectric and spacer dielectric is studied for the first time in RCS-DGJLT. The performance of the device gets improve on increasing the dielectric constant till core thickness (t core) = 3 nm for shell thickness (t shell) = 4 nm. However, beyond core thickness 3 nm, the performance degrades much for high k dielectric. Further, the performance is enhanced for t core > 3 nm and higher k dielectric on reducing the core doping. The device performance is also studied by incorporating the spacers. It has been shown that the device performance is best at t core = 4 nm with low k gate dielectric however, the device performance degrades when high k spacer dielectric is used on the same device which is an interesting and different outcome as compared to conventional DGJLT. The ON current and ON/OFF current ratio are improved by ∼3 orders of magnitude using highly doped source/drain region(HD-S/D) with high k spacers. The results show that the core is the integral part of the device, any engineering like spacers, gate dielectrics applied to RCS-DGJLT requires the optimization of the core carefully for better device performance.

β-Ga2O3 double gate junctionless FET with an efficient volume depletion region

This paper presents a new β-Ga2O3 Junctionless double gate Metal-Oxide-Field-Semiconductor-Effect-Transistor (βDG-JL-FET) with an embedded P+ packet at the oxide layer (PO-βDG-JL-FET) for high-frequency applications. Our goal is to achieve an efficient volume depletion region by placing a P+ layer of silicon. We show that the proposed structure has a subthreshold swing ∼ 64 mV/decade. It suppressed the band-to-band tunneling (BTBT) phenomenon. Also, the PO-βDG-JL-FET design has a high Ion/Ioff ∼ 1.3 × 109. The embedded layer reduces the off-current (IOFF) by ∼ 10−4, while the on-current (ION) reduces slightly. Besides, we show that the proposed structure has an acceptable Ioff value in a range of gate work functions that optimize designs in terms of area, power gain, and leakage current. The proposed structure's leakage current is ∼ 7 × 10−17 A in 400 K temperature. Furthermore, we have shown the fabrication process steps of the proposed design.

FIN Junctionless Field Effect Transistor (FIN-JLFET) with Ground Plane for Surpassing Parasitic BJT Action

The lateral band-to-band tunneling (L-BTBT) leakage mechanism increases the OFF state current and prevents the junctionless transistor from scaling. The effect of L-BTBT on FIN shaped gate Junctionless field effect transistor(JLFET) with the ground plane (GP) in oxide has been investigated. The proposed device is simulated using 3-D Silvaco TCAD and shows that it can mitigate the L-BTBT and leads to efficient volume depletion which relaxes the requirements of ultra-thin silicon thickness and high workfunction of the gate electrode. The results show significantly reduced OFF-state current and high Ion/Ioff ratio even at scaled gate length beyond 10 nm along with the reduction in drain induced barrier lowering and threshold voltage roll-off. Thus, the proposed device shows better performance at sub-10 nm node.

Design and Analysis of a Multi Material Double Gate Junctionless Tunnel Field Effect Transistor

Design and Analysis of a Multi Material Double Gate Junctionless Tunnel Field Effect Transistor

Performance Investigation of Novel Pt/Pd-SiO2 Junctionless FinFET as a High Sensitive Hydrogen Gas Sensor for Industrial Applications

In this paper, a junctionless (JL) Silicon FinFET (Fin Field effect transistor) has been designed as a hydrogen gas (H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) sensor. An analytical model has been developed to analyze the response of junctionless FinFET for detection of hydrogen gas. Palladium is used as a catalytic metal gate. The variation in the gas molecule concentration alters the pressure induced on the catalytic metal gate which changes work function of the metal gate. This variation in metal gate work function is used for detecting the presence of the hydrogen gas. Various electrical parameters for which designed gas sensor is analyzed are- surface potential, threshold voltage, drain current, transconductance, output conductance and charge concentration. The sensitivity analysis in terms of threshold voltage and drain current at different pressures is also carried out. The performance of the sensor with catalytic gate metals-palladium (Pd) and platinum (Pt) is analyzed to find which metal gate gives better response as a hydrogen gas sensor. The JL FinFET is also compared with JL Gate All Around (GAA) transistor for threshold voltage and drain current sensitivity.

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

This article analyses the effect of ion implantation on electrical and circuit-level characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) MOSFET. Ion implantation and subsequent annealing create a Gaussian type doping profile inside the channel. A detailed study of electrical characteristics such as: drain current, threshold voltage, Ion/Ioff, transconductance (gm), output conductance (gd), capacitances (Cgs, Cgd, Cgg), unit gain frequency (fT), transit time (τ), transconductance frequency product (TFP) and gain bandwidth (GBW) product have been performed. Further, an inverter has been designed with a complimentary p-MOSFET and a lookup table-based Verilog-A model has been generated for the same. Various dc and transient parameters such as noise margin, rise time, fall time propagation delay, voltage overshoot, average current, and power dispassion have been analyzed in detail. Henceforth, a 6 T SRAM cell has been implemented with ion-implanted stacked oxide CG-JAM MOSFET and read margin, write margin, access time and N-curve analysis have been performed. Various figures of merits (FOMs) have also been studied for the device at the circuit level. All the device simulations have been performed using a 3-D TCAD tool from COGENDA. Verilog-A model-based circuit simulations have been done in the Cadence-Virtuoso platform.

TCAD-Based Investigation of Double Gate JunctionLess Transistor for UV Photodetector

In this work, TCAD-based investigation of junctionLess (JL) architecture having double gate (DG) has been performed for visualizing the sensitivity of the device against light intensity. Comparison has been drawn between conventional DG MOSFET and DG-JL transistor (DG-JLT) under dark and light conditions. Effect of light intensity and wavelength has been modulated to optimize the device sensitivity. Higher shift in the drain current (in subthreshold region) has been observed at 0.35 μm of wavelength, i.e., more sensitive to ultraviolet (UV) light. The improved sensitivity of DG-JLT as compared to DG-MOSFET is due to the better subthreshold characteristics of the device (i.e., lower leakage current and subthreshold slope). From the results, it can be concluded that the DG-JLT with channel doping of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> , 10 nm of channel thickness, and having 1 nm of oxide thickness is the best possible choice for UV photodetector due to high sensitivity and responsivity. It has also been observed that more optimizing parameters are available with DG-JLT as the DG-MOSFET is immune toward the device parameter variation.

Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ V gs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ V gs = −1 V for L S = L D = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ V gs = 0 V) and tunneling current (2 × 10−8 A @ V gs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ V gs = −1 V), moderate lattice temperature (326) and better I on/I off ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

Triple Metal Surrounding Gate Junctionless Tunnel FET Based 6T SRAM Design for Low Leakage Memory System

The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.

Investigation of Gate Material Engineering in Junctionless Transistor for Digital and Analog Applications

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

A Numerical Investigation of Stacked Oxide Junctionless High K with Vaccum Metal Oxide Semiconductor Field Effect Transistor

The amalgamation of high dielectric permittivity material along with vaccum based dual material junctionless transistor with surrounding gate (DUM-HIK-VAC-JLSG-MOSFET) was investigated in this paper. The diverse oxide gate stack architecture of DUM-HIK-VAC-JLSG-MOSFET abate various effects arise due to channel shrinking. The evaluation of various parameters such as potential distribution in the channel region, electric field (transverse, lateral), transconductance, electron current density and drain current has been analyzed and a comparative statement between DUM-HIK-VAC-JLSG-MOSFET and the single material gate junctionless high k and vaccum double gate MOSFET(SIM-HIK-VAC-JLSG-MOSFET). The commingle of high dielectric permittivity material with vaccum as gate oxide stack and junctionless transistor with surrounding gate structure Dual material achieve a foremost responsibility to mitigate the device shrinking effects, impel to raise the ION current (10−3A/μm) and diminish the leakage current IOFF of 10−18A/μm to boost the ION/IOFF ratio as 1015. To guarantee the scalability and responsiveness of the device simulations has been done with Synopsys TCAD simulator tool.

Performance evaluation of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET using dual material gate engineering

In this paper, the authors present the studies made on drain current (ID) for 5 nm gate length Dual Material (DM) Double Surrounding Gate (DSG) inversion mode (IM) and junctionless (JL) In0.53Ga0.47As nanotube (NT) MOSFET and Silvaco ATLAS 3D TCAD based simulation results are reported. In these studies, the authors have made use of the Non-Equilibrium Green’s Function (NEGF) approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation. In the case of inversion mode nanotube MOSFET, the channel region is lightly doped. The effect of Dual Material Gate Engineering for In0.53Ga0.47As Nano Tube channel radius 1.5 nm with gate oxide (Al2O3) thickness (0.8 nm) on ID, has also been studied. Further, a comparison of results has been done between IM DM DSG and JL DM DSG NT MOSFET. In the case of JL MOSFET, doping concentrations are optimized for two approaches (i) to get the same ION current as IM device and (ii) to get the same threshold voltage (VTH) as IM device. This results in 10 and 102 times smaller IOFF in matching ION and VTH optimized devices respectively as compared to IM device. It was found that DM Gate Engineering reduces drain induced barrier lowering (DIBL) in IM and JL devices. JL device is found to have much smaller DIBL ~ 21.10 mV/V, almost an ideal SS ~ 60 mV/dec, and a higher ION/IOFF ratio ~ 2.85 × 108 as compared to the results available for CGAA devices in the literature.

A Novel Teeth Junction Less Gate All Around FET for Improving Electrical Characteristics

In this paper, we propose a novel “Teeth Junctionless Gate All Around Field Effect Transistor” (TH-JLGAA FET) based on gate engineering method, to obtain finer electrical characteristics. A 3 nm TH-JLGAA FET is designed and was scaled up to 14 nm to observe the effect of scaling on device performance. The characteristics are revealed and compared with contemporary JLGAA FETs. The results show that the novel TH-JLGAA FET appears to have finer Sub-thresholdSlope (SS), Drain Induced Barrier Lowering (DIBL), transconductance (gm), Ion/Ioff current ratio and threshold voltage roll-off. Moreover, these remarkable characteristics can be controlled by engineering the structure and volume of the gate. In addition, the sensitivities of the novel TH-JLGAA FET device with respect to structural parameters are probed.

Analytical Model of Dielectric Modulated Trench Double Gate Junctionless FET for Biosensing Applications

A 2-D analytical model of a dielectric modulated trench double gate junctionless FET (DM-TDGJLFET) is developed for label-free detection of biomolecules. The channel potential is obtained by solving the 2-D Poisson's equation using the parabolic approximation with appropriate boundary conditions. The drain current and threshold voltage are obtained from the minimum channel potential. The proposed DM-TDGJLFET structure has two gates which are vertically placed in separate trenches. The two cavities for biomolecules immobilization are carved in the gate oxide region. The DM-TDGJLFET has been studied for threshold voltage sensitivityof neutral as well as charged biomolecules. For neutral biomolecules, the shift in threshold voltage is obtained as 745mV for change in dielectric constant (k) from 1 to 12. The DM-TDGJLFET performance is also evaluated using commercially available ATLASTM device simulator. The model results show good agreement with simulated data.

Effect of 3 nm gate length scaling in junctionless double surrounding gate SiNT MOSFET by using triple material gate engineering

In this work, drain current ID for 3 nm gate length of triple material (TM) double surrounding gate (DSG) inversion mode (IM) and junctionless (JL) Si nanotube (SiNT) MOSFET has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device we consider the Non Equilibrium Green’s Function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrodinger’s equation. The channel region is lightly doped in case of IM SiNT MOSFET. The effect of TM Gate Engineering for SiNT channel radius 1.5 nm and gate oxide (SiO2) thickness of 0.8 nm on ID, has been studied. Also comparison of results has been done between IM TM DSG and JL TM DSG SiNT. For a reasonable comparison between Junctionless and Inversion Mode SiNT, in Junctionless SiNT, doping concentration is optimized for two concerns (i) to get the same threshold voltage (VTH) as IM SiNT and (ii) to get the same ION current as IM SiNT MOSFET. This results in 103 times smaller IOFF in both matching VTH and ION optimized device as compared to IM SiNT MOSFET. It was found that TM Gate Engineering reduces drain induced barrier lowering (DIBL) in JL SiNT. JL SiNT MOSFET has a smaller DIBL ~ 61.02 mV/V, almost an ideal SS ~ 60 mV/dec and higher ION/IOFF ratio ~ 2.63 × 109 as compared to available CGAA literature device results.

Performance Evaluation of Inversion Mode and Junctionless Dual-Material Double-Surrounding Gate Si Nanotube MOSFET for 5-nm Gate Length

In this work, drain current ID for 5-nm gate length with dual-material (DM) double-surrounding gate (DSG) inversion mode (IM) and junctionless (JL) silicon nanotube (SiNT) MOSFET have been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. For this work, we used the non-equilibrium Green's function (NEGF) approach and self-consistent solution of Poisson's equation with Schrodinger's equation. The conduction band splitting into multiple sub-bands has been considered and there is no doping in channel in case of IM SiNT MOSFET. The effect of DM gate engineering for SiNT channel radius 1.5 nm with 0.8-nm gate oxide (SiO2) thickness on ID has been studied. A comparison of results has been done between IM DM DSG and JL DM DSG CGAA SiNT. In case of JL, doping concentration is optimized for two concerns: (i) to get the same IOn current as IM device and (ii) to get the same threshold voltage VTh as IM. This has resulted in 102 and 103 times smaller IOff in matching IOn and VTh optimized device, respectively, as compared to IM. It is found that DM gate engineering reduces drain-induced barrier lowering (DIBL) for both IM and JL SiNT MOSFET. In this work, JL have much smaller DIBL &amp;#126;15 mV/V, almost an ideal SS &amp;#126;60 mV/dec, and higher IOn/IOff ratio &amp;#126;2.18&amp;#183;108 as compared to available CGAA literature results. Keywords: inversion mode, junctionless, DM DSG, Si nanotube MOSFET, NEGF, ID, SS, DIBL.

Performance assessment of double gate graded junction-less-FET device with temperature variations

This paper reports a simulation-based study of double gate graded channel junctionless metal field effect transistor (MOSFET) incorporating the effects of doping engineering. The proposed device has been optimised to study the effect of temperature on the device characteristics such as surface potential, transfer characteristics, ION/IOFF ratio and, threshold voltage. To justify the enhanced performance of the graded double gate junctionless (DG-JL) FET, it is compared with non-graded DG-JL-FET. To design and optimise the device, the simulation as a tool takes part in understanding of basic physics. The graded DG-JL-FET has better performance over the conventional DG-JL-FET, in terms of ION/IOFF ratio. The temperature effects on various parameters for 1:3 graded structure are obtained and compared with conventional non-graded structure. The shift in potential towards one side and deeper in case of graded structures, IOFF current reduced significantly without affecting ION current. The threshold voltage roll-off with temperature is found slower in graded structure than that in conventional non-graded structure. In this work, visual TCAD simulation tool is used to simulate the electrical characteristics of the proposed device.

Investigation of tied double gate 4H–SiC junctionless FET in 7 nm channel length with a symmetrical dual p+ layer

In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect (DG-JLFET) transistors with a symmetrical dual p + layer (S-D-P DG-JLFET) and the proposed structure compared with a conventional junctionless tied double gate field effect structure (DG-JLFET). By changing the depletion region in the proposed structure and due to the symmetrical dual p + layer, off-current and drain induced barrier lowering (DIBL) effect is improved but on-current reduces a bit. In our paper, we discuss the work function effect on the off and on-current. Also, the effects of temperature on the electron mobility, the threshold voltage, and changing the lengths of the added p + layers have been investigated. Due to the design complexity of the devices in sub 20-nm, the proper models are considered. The ratio of the I on /I off current of the proposed structure improves significantly versus the conventional double gate junctionless FET. • Improvement in properties of semiconductor physique. • Improvement of control on carrier concentration by gate electrode. • Enhancement of depletion region and better leakage current.

Analytical modelling and verification of potential profile of DG JLFET with and without stack oxide

ABSTRACT In this paper, a physically based two-dimensional analytical model of potential profile is proposed for both symmetric and asymmetric p-type-doped Double Gate Junctionless Field Effect Transistors (DG JLFETs). The proposed model keeps its validity in the subthreshold region. In order to establish the model, 2-D Poisson’s equation is solved in the channel region while assuming cubic potential distribution along the channel region. We also propose a 2-D analytical model of symmetric Double Gate Stack-Oxide Junctionless Field Effect Transistors (DGS JLFETs). In order to check out the validity of our proposed model, we have used SILVACO ATLAS simulator. Comparison of potential distribution is made between different structures. Between symmetric and asymmetric structures, symmetric structure shows better potential profile as they have shown higher potential distribution in channel region. But when DG JLFET is compared with DGS JLFET, we find better potential profile distribution in DGS JLFET. Important performance parameters like Ion/Ioff ratio, SS, DIBL, Threshold Voltage, I–V characteristics for different structures are found out and compared among them. Asymmetric structure with same electrode materials in both gates but having lower bottom gate oxide thickness showed better performances like higher Ion/Ioff ratio, lower SS, less DIBL compared to other DG JLFETs with and without stack oxide.