Effect of 3 nm gate length scaling in junctionless double surrounding gate SiNT MOSFET by using triple material gate engineering

Abstract

In this work, drain current ID for 3 nm gate length of triple material (TM) double surrounding gate (DSG) inversion mode (IM) and junctionless (JL) Si nanotube (SiNT) MOSFET has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device we consider the Non Equilibrium Green’s Function (NEGF) approach and self-consistent solution of Poisson’s equation with Schrodinger’s equation. The channel region is lightly doped in case of IM SiNT MOSFET. The effect of TM Gate Engineering for SiNT channel radius 1.5 nm and gate oxide (SiO2) thickness of 0.8 nm on ID, has been studied. Also comparison of results has been done between IM TM DSG and JL TM DSG SiNT. For a reasonable comparison between Junctionless and Inversion Mode SiNT, in Junctionless SiNT, doping concentration is optimized for two concerns (i) to get the same threshold voltage (VTH) as IM SiNT and (ii) to get the same ION current as IM SiNT MOSFET. This results in 103 times smaller IOFF in both matching VTH and ION optimized device as compared to IM SiNT MOSFET. It was found that TM Gate Engineering reduces drain induced barrier lowering (DIBL) in JL SiNT. JL SiNT MOSFET has a smaller DIBL ~ 61.02 mV/V, almost an ideal SS ~ 60 mV/dec and higher ION/IOFF ratio ~ 2.63 × 109 as compared to available CGAA literature device results.