Performance evaluation of junctionless double surrounding gate In0.53Ga0.47As nanotube MOSFET using dual material gate engineering

Abstract

In this paper, the authors present the studies made on drain current (ID) for 5 nm gate length Dual Material (DM) Double Surrounding Gate (DSG) inversion mode (IM) and junctionless (JL) In0.53Ga0.47As nanotube (NT) MOSFET and Silvaco ATLAS 3D TCAD based simulation results are reported. In these studies, the authors have made use of the Non-Equilibrium Green’s Function (NEGF) approach and the self-consistent solution of Poisson’s equation with Schrodinger’s equation. In the case of inversion mode nanotube MOSFET, the channel region is lightly doped. The effect of Dual Material Gate Engineering for In0.53Ga0.47As Nano Tube channel radius 1.5 nm with gate oxide (Al2O3) thickness (0.8 nm) on ID, has also been studied. Further, a comparison of results has been done between IM DM DSG and JL DM DSG NT MOSFET. In the case of JL MOSFET, doping concentrations are optimized for two approaches (i) to get the same ION current as IM device and (ii) to get the same threshold voltage (VTH) as IM device. This results in 10 and 102 times smaller IOFF in matching ION and VTH optimized devices respectively as compared to IM device. It was found that DM Gate Engineering reduces drain induced barrier lowering (DIBL) in IM and JL devices. JL device is found to have much smaller DIBL ~ 21.10 mV/V, almost an ideal SS ~ 60 mV/dec, and a higher ION/IOFF ratio ~ 2.85 × 108 as compared to the results available for CGAA devices in the literature.