Abstract
The promising capability of Triple Material Surrounding Gate Junctionless Tunnel FET (TMSG – JL – TFET) based 6 T SRAM structure is demonstrated by employing Germanium (Ge) and High-K gate dielectric material. The high – K insulation guarantees the proposed device to be used in low leakage memory systems. The corresponding analytical model is developed to extract various device parameters such as surface potential, electric field and threshold voltage. The results yield minimization of hot carrier effects at the drain end, when compared to conventional Silicon (Si) based Tunnel FETs (TFETs). Further, the ambipolar characteristics of the proposed device is explored and 6 T Ge – TMS – SG – JL – TFET based SRAM design is proposed. The results are compared with CMOS based SRAM and the analytical model presented is validated using 3D - TCAD ATLAS simulation, which ensures the accuracy and exactness of the developed model.
Highlights
The intense development of channel engineering and manufacturing technology to obtain better efficiency has successfully driven continued device scaling
The proposed Ge based Triple Material Surrounding Gate (TMSG)-Junctionless TFET (JLTFET) has incorporated the effect of high-K material and renders superior value of surface potential compared to Si based device with silicon dioxide as their gate - oxide material
To validate and verify our model, the proposed mathematical expressions have been related with silicon based TMSG-JLTFET and with the results extracted from 3-D Silvaco ATLAS TCAD simulator
Summary
The intense development of channel engineering and manufacturing technology to obtain better efficiency has successfully driven continued device scaling. In order to further enhance the device efficiency in terms of reduced SCEs [1], engineers in the field of nanotechnology have been researching and looking for new device architectures In this concern, Junctionless FETs (JLFETs) [2 - 4] have been the most influential device in rendering decreased SCEs, high ON – OFF current ratio and almost ideal subthreshold slope (SS ∼ 60 mV/dec). The analytical model for junctionless DMDG FET [9] is proposed, but the aggregate advantages of Ge, High-K gate dielectric [17 - 19] (Titanium Oxide - TiO2), and triple material gate work function engineering has not been explored in short channel (12nm) junctionless surrounding gate tunnel FETs [20 – 22]. In order to observe the short channel effects, the surface potential and electric field are critical components and can be estimated by solving the 2-D Poisson's equation by parabolic approximation. Components of the electric - field LEi(z), lateral electric - field and VEr(z), vertical electric - field are represented as: V_bip Cosh( z) Cosh( (z L _i ))
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