3-D analytical modeling of dual-metal front-gate stack tri-gate SON-TFET with graded channel engineering

Abstract

An explicit 3-D analytical surface potential modeling of Dual Metal Front Gate Stack triple-gate silicon-on-nothing Tunnel Field Effect Transistor with the concept of Graded channel (GC-DMTG SON-TFET) is presented in this work to explore the triple benefits of gate, dielectric and channel engineering techniques. Surface potential and electric field functions have been formulated using suitable boundary conditions in 3-D Poisson's equation to study the nature of these plots in terms of various short channel effects. Finally, the drain current profile has been derived finding the shortest tunneling path using the potential distribution at the source end and average electric field along the shortest tunneling path in the Kane's model. The performance of the proposed device is compared with Dual-Material Tri-Gate SON TFET to establish the superiority of the structure. Total electric field profile closer to drain end is examined to vindicate the immunity of the device towards hot carrier effect. Step profiles in both surface potential and electric field for the proposed geometry reveal better screening of the device towards drain bias variation. The 3-D analytical results are simulated using Silvaco ATLAS to fulfill the accuracy of the present analytical model.