Performance Analysis of Emerging Low-Power Junctionless Tunnel FETs

Abstract

Continued scaling of devices has been strongly influenced by the recent advancements in channel engineering and device fabrication technology for realizing improved performance. As the device dimensions are continuously shrinking,the gate loses its complete control over the channel, and this leads to numerous short-channel effects (SCEs). Nanotechnology device engineers have been investigating and searching for novel device structures to further improve the performance of the device in terms of reduced SCEs. In this regard, a quantum tunneling-based field-effect transistor (FET) known as tunnel FET (TFET) has evolved as a promising candidate that has several advantages such as diminished SCEs and high I ON/I OFF ratio and subthreshold swing (SS) less than 60 mV/decade. Also, the concept of work function engineering in the gate metal region is another phenomenal solution to reduce the SCEs. A dual material double-gate (DMDG) TFET structure employs two gate materials with different work functions placed side by side to introduce a step-like profile in the channel. Hence, various research works are in progress to improve the subthreshold characteristics of a device with enhanced oxide interface. High-K gate dielectric materials can be treated as the best solution for concurrent minimization of gate leakage current. However,Si-based TFETs and SiO2 as a gate dielectric resulted in poor electrostatics, and a very high gate voltage is required for TFET operation. Also,the gate leakage current will be very large,exceeding1 A/cm2 at 1 V, which is due to the tunneling of electrons through the SiO2 layer. To overcome these scaling limitations,a junctionless metal oxide semiconductor field-effect transistor (MOSFET) (JLFET) was proposed. The doping concentration of these JL transistors is uniform throughout the device. This uniform doping helps the JL FETs to eliminate the formation of source/channel and channel/drain junctions. Dual material double-gate JLTFET (DMDG JLTFET) with a stacked/heterodielectric gate-oxide structure is proposed. The high-K gate stack engineered device overcomes the SCEs caused by the ultrathin silicon devices. With gate work function engineering and titanium oxide (TiO2) as gate dielectric, the proposed device will have better control over the vertical field, thereby reducing the penetration of hot electrons through the gate oxide and improving the device performance. A comparative analysis of SCEs for DMDG TFET and DMDG JLTFET has been carried out. The results reveal that the proposed device provides better ION current, low leakage current, and improved transconductance-to-drain-current ratio.