Abstract
In this work, we present a novel ultra-thin 4H–SiC junctionless tied double gate field effect (DG-JLFET) transistors with a symmetrical dual p + layer (S-D-P DG-JLFET) and the proposed structure compared with a conventional junctionless tied double gate field effect structure (DG-JLFET). By changing the depletion region in the proposed structure and due to the symmetrical dual p + layer, off-current and drain induced barrier lowering (DIBL) effect is improved but on-current reduces a bit. In our paper, we discuss the work function effect on the off and on-current. Also, the effects of temperature on the electron mobility, the threshold voltage, and changing the lengths of the added p + layers have been investigated. Due to the design complexity of the devices in sub 20-nm, the proper models are considered. The ratio of the I on /I off current of the proposed structure improves significantly versus the conventional double gate junctionless FET. • Improvement in properties of semiconductor physique. • Improvement of control on carrier concentration by gate electrode. • Enhancement of depletion region and better leakage current.
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