Gate-all-around Research Articles

Steep Switching Si Nanowire p-FETs With Dopant Segregated Silicide Source/Drain at Cryogenic Temperature

Fully silicided source/drain Si gate-all-around (GAA) nanowire (NW) p-FETs with NW diameter of 5 nm are fabricated and characterized from room temperature (RT) down to 5.5 K. Thanks to the improved electrostatics by the scaled NW and 3D GAA structure, close to ideal transfer characteristics are obtained at both RT and 5.5 K with a sharp switching. Benefiting from less defects in Si created by the implantation into silicide (IIS) process, the band tail effects and neutral defects scattering are suppressed. Therefore, the fabricated Si GAA NW p-FETs provide very low subthreshold swing SS of 3.4 mV/dec in the weak inversion region and an average SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> of 14 mV/dec measured from the off-state to the threshold voltage, as well as an improved transconductance G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> at 5.5 K.

Electrical Characteristics of In0.53Ga0.47As Gate-All-Around MOSFETs With Different Nanowire Shapes

In this article, we investigate the electrical properties of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As gate-all-around (GAA) MOSFETs with different nanowire shapes. InGaAs GAA MOSFETs with trapezoid and triangle nanowire shapes have been fabricated and characterized. Improved output performance was observed as the nanowire top width reduces from 20 to 11 nm. It was found that the electrical characteristics degraded as the nanowire top width was decreased to nearly 0 nm. To explain the carrier transport mechanism in ultralow-scale devices, TCAD simulation has been performed to study the electron density distribution for different nanowire widths and explain the transport mechanism in these ultralow-scale transistor devices.

3D Nanoscale Imaging of Semiconductor Films for GAA (Gate All Around) Device Development

3D Nanoscale Imaging of Semiconductor Films for GAA (Gate All Around) Device Development

Demonstration of Temperature-Dependent Analysis of GAA – β-(AlGa)2O3/Ga2O3 High Electron Mobility Transistor

In this work, we have, designed and demonstrated Gate all around (GAA)-β-AGO/GO HEMT to achieve large current density, electron mobility and electron velocity at cryogenic temperatures. Because the controlling of the gate is better in GAA-based structures the performance of the proposed device is magnified for a different temperature range. The 2DEG channel mobility of the proposed device is boosted from 130 cm2/Vs at 300 K to 4100 cm2/Vs at 50 K. Mobility of the proposed device is boosted from the previous value by the factor of 2.5 at room temperature. The higher electron mobility at lower temperatures made it suitable to reach a larger saturation velocity center of the channel. Analog, RF and linearity parameters are analyzed with different temperature ranges at a gate length of 0.9 µm. The drain current and cutoff frequency of the device is 750 mA/mm and 18 GHz, respectively at 50 K and it reduces for a larger temperature. The breakdown voltage of the proposed device at 300 K is 139 V. The noise analysis is also taken for the investigation of its random nature. This type of device is used in power-switching applications.

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets.

A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring oscillator (RO) gained up to 27.8% improvement of delay with the same power consumption, for a 3-layer stacked GAA NS-FETs. Furthermore, the proposed S/D trimming technology could enable more than 4-layer vertical stacking of nanosheets for GAA technology extension beyond 3 nm CMOS technology.

(Digital Presentation) Diffusion and Segregation in Highly Stacked Ge0.9Sn0.1/Ge:B and Ge0.95Si0.05/Ge:P Epilayers

GeSn and GeSi are promising channel materials for gate-all-around (GAA) devices to achieve the high ION thanks to the high mobility [1, 2]. The undoped channels are used to reduce the impurity scattering and to further enhance the mobility. The GAA structure with high number of stacked channels can further enhance the ION for a fixed footprint. The dopant diffusion and segregation play an important role on GAA device structure design. In this work, the dopant diffusion and segregation effects of B and P in highly stacked Ge0.9Sn0.1 and Ge0.95Si0.05 epilayers are investigated, respectively.The Ge:B/Ge0.9Sn0.1/Ge:B epilayers were grown on the Ge-buffered SOI substrate at 320°C and 100 torr by chemical vapor deposition (CVD) using SnCl4, Ge2H6, and B2H6 precursors. The 160nm undoped Ge buffer was grown with an 800℃ annealing to confine the misfit dislocations at Ge/Si interface. For the 8 stacked Ge0.9Sn0.1 epilayers, 36 nm Ge0.9Sn0.1 layers sandwiched by 24 nm Ge:B layers were grown. Transmission electron microscopy (TEM) image of Ge:B/Ge0.9Sn0.1/Ge:B epilayers is shown in Fig. 1(a). The Ge:P/Ge0.95Si0.05/Ge:P epilayers were grown on the Ge-buffered SOI substrate at 350°C and 100 torr by SiH4, GeH4, and PH3 precursors using similar Ge buffer layers. For the 8 stacked Ge0.95Si0.05 epilayers, 24 nm Ge0.95Si0.05 layers sandwiched by 25 nm Ge:P layers were grown. TEM image of Ge:P/Ge0.95Si0.05/Ge:P epilayers is shown in Fig. 1(b). Note that both Ge0.9Sn0.1 and Ge0.95Si0.05 channel layers are unintentionally doped. In the 8 stacked Ge0.9Sn0.1 epilayers, the [B] in the Ge:B layers is as high as ~2.0 ×1021 cm−3 (Fig. 2(a)). In the 8 stacked Ge0.95Si0.05 epilayers, the [P] in the Ge:P layers is as high as ~2.2 × 1020 cm−3 , and the minimum [P] in the Ge0.95Si0.05 channel layers is from ~4.2 ×1017 cm−3 to ~1.5 ×1018 cm−3 (Fig. 2(b)).The B and P diffusion phenomena in the GeSn and GeSi layers are investigated, respectively. The deep undoped GeSi layers have higher [P] due to higher thermal budget (Fig. 3). Note that the P atoms diffuse from the Ge:P layers into GeSi channels during the epitaxial growth. The similar [B] ~3x1016cm-3 in the 2nd to 8th GeSn layers is due to the B detection limit of SIMS analysis (Fig. 3). Note that the decay length (nm/decade) is defined in Fig. 4 and Fig. 5. The decay length of [B] on the top side (4.3 nm/decade) is larger than that on the bottom side (2.9 nm/decade) due to SIMS knock-on effect [3] (Fig. 4). On the other hand, the P segregation [4] increases the decay length on the bottom side of GeSi layers (Fig. 5). Both the decay length of [B] and [P] increase with the increasing depth (Fig. 6) due to the higher thermal budget of the deeper layers in the CVD chamber. In addition, the difference of [B] decay length between top and bottom sides increases with the increasing depth of epilayers (Fig. 6). For the Ge:P/GeSi/Ge:P epilayers, the difference between top and bottom [P] decay length (less than 0.9 nm/decade) is smaller than that of [B] decay length in Ge:B/GeSn/Ge:B epilayers (larger than 1.4 nm/decade) due to P segregation, and the difference decreases for deep layers.AcknowledgmentThis work is supported by the Ministry of Science and Technology, Taiwan (MOST 110-2622-8-002-014-, 110-2218-E-002-030-, and 110-2218-E-002-042-MBK) and the Ministry of Education, Taiwan (NTU-CC-110L892601). The support by Taiwan Semiconductor Research Institute (TSRI), Hsinchu, Taiwan, is also highly appreciated.

(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling

CMOS scaling has been the backbone of the overall logic roadmap for decades, but it is reaching its physical limits while also imposing ever more constraining design restrictions. This has triggered a critical need for new device architectures and integration concepts to be able to continue delivering profitable node-to-node scaling gains and to help preserve the industry’s power-performance-area-cost metrics. From the transistor’s perspective, vertically stacked lateral nanosheet (NS) FETs, with a gate-all-around (GAA) configuration, are widely regarded as the most promising and mature option to replace finFETs. Reduced gate lengths should be feasible thanks to their improved electrostatics, thus allowing further scaling of the contacted-gate-pitch and of the cell height via a reduced number of metal tracks. Other key characteristics include high design flexibility, with various NS widths possible on a given wafer, and larger drivability per layout footprint by increasing the number of vertically stacked NS per device and/or using wider NS [1,2] (Fig.1). An extension of this technology could in principle be envisioned by strongly reducing the p-n separation in the so-called forksheet configuration [3]. Beyond that, the concept of stacking devices with different polarity on top of each other is also being looked at [4,5]. Other future technology candidates include FETs with vertical transport [6] and non-silicon channels [7]. Each new architecture will have its own specific challenges such as the internal routeability for stacked structures in functional logic blocks (e.g., standard cell or SRAM) but, in general, many elements can be shared by the various branches of the NS family of devices.Overall, a careful balance between drive strength and capacitance is required in NS FETs engineering. In particular, the presence of dielectric inner spacers in-between vertically stacked nanosheets is a critical element, also as it leads to a different growth regime for the source/drain (S/D) epi as compared to the situation in finFETs [8]. This is an important differentiator as channel strain induced by S/D has been traditionally used to boost device performance. The feasibility of continuing using process-induced stress techniques for mobility enhancement is in fact a key challenge for several new architectures, namely for the top device in stacked structures or when S/D are placed in different vertical levels. Moreover, faced with power scaling stagnation, cold computing is also becoming an attractive option to consider for enabling high performance boosting in an energy efficient way. Our results confirm improved DC properties for NS FETs (e.g., subthreshold swing (SS), mobility), with similar mechanisms responsible for their noise behavior at room and low temperatures (300K (RT), 78K) [9].In addition to the need for the introduction of new transistor technologies, given the increased complexity and cost in back-end-of-line processing, it has also become ever more pressing to address both wiring and power delivery network (PDN) bottlenecks to take full advantage of the scaling performance benefits at transistor level. The concept of moving the PDN to the wafer’s backside (BS) such that it can alleviate routing congestion on its frontside (FS) has been recently gaining traction [10,11]. This is illustrated in Fig.2 wherein, by combining logic and 3D technologies, both wafer sides are used. In our work, after frontside processing, device and carrier wafers are bonded at RT, including a 523K post-bond anneal. Extreme wafer thinning is then implemented prior to nano-through-silicon-vias (n-TSV) definition (landing on the metal-1 level (M1) in the frontside) and backside metallization. Evaluating the impact on scaled transistors from BS processing, our results show similar p/n threshold voltages (VTs) can be obtained with an extra sinter at the end of fabrication. Inclusion of an additional high-pressure H2-anneal prior to the final sinter is also seen to help lower the SS values for pmos without significant IOFF effect. Reliability-wise, constant ramped voltage stress measurements also show no BTI degradation for p/nmos, with additional indication of potential benefits by the final anneal(s) treatment selection. These findings are further corroborated by LF-noise analysis.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

(Invited) Characterization of Wetting Behavior on High Aspect Ratio Multilayer Structure

The miniaturization and complexity of semiconductor structures increase to improve device performance and functionality. In particular, the latest high-performance semiconductor architectures are formed of high-aspect-ratio structures composed of multilayer thin films. In the case of logic devices, it is reported that the gate-all-around(GAA) structure will become the mainstream, and in the 3D NAND flash memory, it will have a structure with more than 168 layers and a high aspect ratio of 50 or more. In order to form such a structure, the manufacturing process becomes complicated and various challenges to be solved occur. One of the challenges facing is efficiently removing contaminants generated while forming structures having a complex and high aspect ratio structure without damaging the structures. In the case of a wet cleaning process, a technology capable of removing only contaminants without pattern collapse and material loss is required.In order to develop a wet cleaning process for effective contaminant removal and precise control in cleaning process on a high aspect ratio multilayer structure, it is necessary to understand the chemical reaction characteristics between the material and the cleaning chemicals. In particular, it is important to understand the wettability of the cleaning liquid in the structures for damage-free cleaning process development.The wettability of HAR nanostructures was studied using the FTIR-ATR measurement technique. Studies have shown that FTIR-ATR is a reasonable method for studying the wettability properties in HAR structures made of Si. We performed similar experiments and similar experimental results were obtained. However, the FTIR-ATR analysis method is difficult to apply to a HAR multilayer structure. In this structure in which thin films with different optical properties are stacked, the IR signal did not reach the detector sufficiently, making measurement impossible. In this paper, we introduce a new measurement method for analyzing the wettability in the HAR multilayer structures.To evaluate the wettability of various chemicals in HAR multilayer structures, the trench pattern with a width of 200 nm and a depth of 9500 nm, the aspect ratio of 47.5 was used. This sample was immersed in a 20 nm silica particle solution to observe the arrival depth of the particles in the trench. To visualize the particle arrival depth, the sidewall of the trench was exposed by cutting and the sidewall surfaces were characterized by atomic force microscope (AFM, NX-20, Park Systems, Korea). Furthermore, an organic thin film which was carried out to form a hydrophobic surface was deposited on the samples to observe the wetting behavior according to the various wettability of the trench surface. A hydrophobic surface with a water contact angle of 95° was formed on the sample by depositing an organic thin film to observe the wetting behavior according to various wetting properties of the trench surface. The surface tensions of the particle solutions were varied by adding SDS surfactant.The change in the sidewall surface of the trench using AFM was visualized successfully, and the observation explained the wetting behavior of the liquid. The experimental results agreed with the values calculated by the Wenzel & Cassie-Baxter model. The visualization of the trench sidewall using AFM could help understand the wetting behavior in the HAR multilayer structure.

A Machine Learning Approach for Optimization of Channel Geometry and Source/Drain Doping Profile of Stacked Nanosheet Transistors

Complex nonlinear dependence of ultra-scaled transistor performance on its channel geometry and source/drain (S/D) doping profile bring obstacles in the advanced technology path-finding and optimization. A machine learning-based multi-objective optimization (MOO) workflow is proposed to optimize the sub-3-nm node gate-all-around (GAA) three-layer-stacked nanosheet transistors (NSFETs) accounting for the key performance knob of channel geometry and S/D doping profile. The artificial neural network (ANN) is trained to learn the compact current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> ) relationship of NSFETs from 3-D technology computer-aided design (TCAD) simulation results. Based on the artificial neural network (ANN) model, MOO between threshold swing, on–off ratio, and ON-state current of NSFETs is performed with adaptive weighted sum theory. The proposed workflow efficiently suggests an optimized design window of channel geometry and doping profile of NSFETs. The proposed devices satisfy the 2025 International Roadmap for Devices and Systems (IRDSs) target in terms of electrical characteristics for digital circuits.

Impact of Process Variation on Nanosheet Gate-All-Around Complementary FET (CFET)

In this work, dc characteristic variations of nanosheet (NS) gate-all-around (GAA) complementary FET (CFET) induced by process fluctuations are investigated for the first time. Four process variability sources including work-function variation (WFV), line edge roughness (LER), gate edge roughness (GER), and random dopant fluctuation (RDF) are characterized. Compared to the conventional NA GAA FET, the differences mainly exist in GER. The electrostatic potential variation induced by GER in CFET is affected by both the common metal gate and the additional p-type work-function (p-WF) liner for p-FET. Therefore, the impact of GER on p-FET is much larger than n-FET as well as conventional NS GAA FET. Thickening the p-WF liner is proposed to overcome the drawback. Calculated overall variations considering all process fluctuation sources are also discussed, highlighting the impact of the dual-WF gate on p-FET. The results are helpful for the characterization and optimization of variations in CFET and precise CFET-based circuit design.

TID Effects in Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors Irradiated to Ultrahigh Doses

Total-ionizing-dose (TID) effects are investigated in a highly-scaled gate-all-around (GAA) FET technology using Si nanowire channels with a diameter of 8 nm. n- and p-FETs are irradiated up to 300 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ). At ultrahigh doses, the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -driven generation of interface traps at the oxide/channel interface. In contrast, FETs irradiated under negative gate bias are dominated by transconductance loss and increases of low-frequency noise, suggesting the activation of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions.

Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness

A comprehensive subthreshold model of asymmetric gate all around (GAA) junctionless (JL) FETs with scaled equivalent oxide thickness is developed in the work. The perimeter weighted sum approach is implemented to model the channel potential and threshold voltage of the device. Further, a novelty in the perimeter weighted approach is proposed to model subthreshold slope of the device. With the proposed novelty appended, the perimeter weighted approach can present a complete subthreshold solution of three dimensional multi-gate devices. Silicon dioxide, Silicon nitride, and stack of Hafnium oxide with interfacial Silicon dioxide are implied as gate dielectric to study the scaling of equivalent oxide thickness of the device in sub-1nm domain. The device characteristics for asymmetric GAA structure imparted due to the dielectric thickness asymmetry have been studied. The numerical results are compared with 3D Sentaurus TCAD device simulation outputs for variation in device parameters.

Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved.

Characteristics Extraction of Fully Symmetric GAA and Top-Gate CNTFETs with 6 nm Channel Length

High-compatible applications for top-gate and gate-all-around (GAA) carbon nanotube field-effect transistors (CNTFETs) are presented. The geometrical specifications of these CNTFETs are evaluated and their effects on the characteristics are highlighted. The channel length is considered 6 nm, while the drain, source, and spacer are symmetric with channel length. The evaluations are performed by the COMSOL Multiphysics, and the Shockley-Read-Hall (SRH) recombination model is used to analyze doping, electron, and hole distributions. The drain and source wells are considered with donor doping of ND0 = 1 × 1021 cm−3 and acceptor doping of NA = 1 × 1019 cm−3, then, the current-voltage (I–V) characteristics are extracted. Also, the CNTs with 1.12 nm are placed accurately through the channel, and the terminals are constructed with graphene. The I–V curves show that the threshold voltage for the top-gate and GAA are 0.23 V and 0.21 V, respectively. Besides, the short channel effect (SCE) is reduced which is confirmed by a subthreshold swing (SS) of 62 mV/dec for the top-gate and 58 mV/dec for the GAA. Moreover, drain-induced barrier lowering (DIBL) and ION/IOFF ratio parameters are studied to investigate scaled-down devices. The discussed structures are compared by the figure of merit (FoM) of ΔVDIBLSS/(ION/IOFF), which shows more desirable and better channel control. The temperature variations show that there is no dramatic increase in the leakage current, which proves that symmetric structure is reliable in short-channel devices.

Vertical 3D diamond field effect transistors with nanoscale gate-all-around

Recent studies have shown that diamond field effect transistors (FETs) have great potential in high-power and high-frequency electronics, exhibiting the maximum leakage current of 1.35 A·mm−1 and the breakdown voltage of 2 kV. However, there is still a lack of preliminary exploration on diamond FETs with a three-dimensional (3D) architecture, which has been evidenced as a promising approach to increase device performance and density for silicon transistors. In this paper, we present a systematic investigation of 3D vertical gate-all-around (GAA) diamond transistors, combined with numerical simulation, device fabrication and characterization of device performance. The p-type conductivity of the diamond channel in a transistor is obtained by Boron-ion implantation. Our numberical simulations address the close correlation of transfer characteristics of the 3D vertical GAA diamond transistors with the ion implanted impurities. In the device fabrication, we introduce the focused ion and electron beam technology for the electrode interconnections in the 3D devices. Finally, we demonstrate that the 3D vertical GAA diamond transistor exhibits the on-off ratio of 2.5 × 103, subthreshold swing of 334.3 mV·dec−1, and threshold voltage of 0.64 V. And the temperature dependence of transfer characteristics of the 3D devices indicates that 3D vertical GAA diamond transistors have potential application prospects in extreme environments such as high temperature.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an I on/I off-ratio of 2.1×106 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.

DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets

DC and low frequency noise measurements are performed in p-channel gate all around (GAA) vertically stacked silicon nanosheets (NS) at room temperature. The key DC parameters such as threshold voltage, low field mobility, access resistance and subthreshold swing are estimated. Preliminary low frequency noise studies reveal that the 1/f noise may be explained in weak to moderate inversion by the carrier number fluctuation mechanism, while in strong inversion the access resistance noise prevails.

Review of nanosheet metrology opportunities for technology readiness

Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured the focus of the semiconductor industry and have been identified as the lead architecture to continue logic complementary metal-oxide-semiconductor scaling beyond 5 nm node. The fabrication of GAA devices requires specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology progresses through research and development cycles and is poised to transition to manufacturing, there are many opportunities and challenges that still remain for in-line metrology. Especially valuable are measurement techniques that are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact on the frequency of cycles of learning. More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. Thanks to the computing revolution the semiconductor industry enabled, machine learning has begun to permeate in-line disposition, and hybrid metrology systems continue to advance. Of course, metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness, pitch walk, and defectivity continue to be managed. We review related prior studies and advocate for future metrology development that ensures nanosheet technology has the in-line data necessary for success.

Impact of the channel doping on the low-frequency noise of silicon vertical nanowire pFETs

In this work, the impact of the channel doping on the low-frequency noise of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) pMOSFETs on Silicon-on-Insulator (SOI) substrates will be described and discussed. It is demonstrated that the dominant fluctuation mechanism of the 1/f noise in weak inversion changes from mobility (Δμ) to number (Δn) fluctuations with increasing doping density of the silicon nanowires. At the same time, the lowest input-referred voltage noise Power Spectral Density is observed for an intermediate boron concentration of 5 × 1018 cm−3.