Vertical 3D diamond field effect transistors with nanoscale gate-all-around

Abstract

Recent studies have shown that diamond field effect transistors (FETs) have great potential in high-power and high-frequency electronics, exhibiting the maximum leakage current of 1.35 A·mm−1 and the breakdown voltage of 2 kV. However, there is still a lack of preliminary exploration on diamond FETs with a three-dimensional (3D) architecture, which has been evidenced as a promising approach to increase device performance and density for silicon transistors. In this paper, we present a systematic investigation of 3D vertical gate-all-around (GAA) diamond transistors, combined with numerical simulation, device fabrication and characterization of device performance. The p-type conductivity of the diamond channel in a transistor is obtained by Boron-ion implantation. Our numberical simulations address the close correlation of transfer characteristics of the 3D vertical GAA diamond transistors with the ion implanted impurities. In the device fabrication, we introduce the focused ion and electron beam technology for the electrode interconnections in the 3D devices. Finally, we demonstrate that the 3D vertical GAA diamond transistor exhibits the on-off ratio of 2.5 × 103, subthreshold swing of 334.3 mV·dec−1, and threshold voltage of 0.64 V. And the temperature dependence of transfer characteristics of the 3D devices indicates that 3D vertical GAA diamond transistors have potential application prospects in extreme environments such as high temperature.