Subthreshold model of asymmetric GAA junctionless FETs with scaled equivalent oxide thickness

Abstract

A comprehensive subthreshold model of asymmetric gate all around (GAA) junctionless (JL) FETs with scaled equivalent oxide thickness is developed in the work. The perimeter weighted sum approach is implemented to model the channel potential and threshold voltage of the device. Further, a novelty in the perimeter weighted approach is proposed to model subthreshold slope of the device. With the proposed novelty appended, the perimeter weighted approach can present a complete subthreshold solution of three dimensional multi-gate devices. Silicon dioxide, Silicon nitride, and stack of Hafnium oxide with interfacial Silicon dioxide are implied as gate dielectric to study the scaling of equivalent oxide thickness of the device in sub-1nm domain. The device characteristics for asymmetric GAA structure imparted due to the dielectric thickness asymmetry have been studied. The numerical results are compared with 3D Sentaurus TCAD device simulation outputs for variation in device parameters.